pio timing problem

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

pio timing problem

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Hi,

i write a 32 bit value coming from a sinc3 filter into my pio register. From there i read it into my nios system using the IORD_ALTERA_AVALON_PIO_DATA(BASE) command. According to the Performance Counter this reading process takes about 1000clock ticks.

I already added an additional output register to my filter. I have added the filter vhdl code as an Attachement.

The nios system clock is 50MHz. The filter clocks are: MCLK = 10MHz and CNR = 39kHz. With this Setting the fir has a filter Response time of 76us.

Thanks for help!

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