preserve_hierarchy assignment

[Altera_Forum]

Hi,  

It seems like Preserve_hierarchy assignment doesn't work in my Quartus. My components are merged together (i don't want that). I could see it (one of my components) in RTL view but I couldn't find it in post-map technology view. Anyone has same problem?  Thanks a lot.

[Altera_Forum]

Hello , 

 Do you prefer VHDL ? I am a VHDL user And I prefer to use Attibute to keep the node in Logic Design instead of setting the "preserve register" assignment in the Q II Assignment Editor  This applicable to all register nodes There are two useful attributes which are "syn_preserve" and "syn_keep"  syn_preserve is used for keeping the register node , avoid being synthesized away syn_keep is used for keeping the net , to my understanding (I am not sure if it's correct) , it keeps the node so that user can find the node in node finder , but it doesnt guarantee the logic is kept there.  Usually I focus on the register nodes and I do not care about those combinational nodes in the design  Here is an example :  In the signal declaration part : signal Din_p0 : std_logic_vector(15 downto 0); attribute syn_preserve : boolean; attribute syn_preserve of din_p0 : signal is true;  Then the Din_p0 will be preserved  Another Example signal Q0 : std_logic; signal Q1 : std_logic;  begin   process (clk, A, B)  begin  if clk = '1' and clk 'event then  Q0 <= A and B;  Q1 <= A and B;  end if;  end process;  end behavioral;  Then Quartus will preserve DFF for node Q0 and node Q1  Hope it helps Samson

[Altera_Forum]

preserve and keep attributes are grest for specific signals that you want to see after optimization. 

 Another way to preserve the entire hierarchical boundary very strictly is to define the blocks as separate partitions for incremental compilation. In Project Navigator, right-click > Set as Design Partition. You don't have to make any settings for the Design Partitions if you don't care about preserving fitter results, but know that by default post-synthesis results are reused in the next compile unless you change the source code (that is, settings do not trigger recompilation).   Note that making them partitions will prevent *any* cross-boundary optimizations including constant connections or unused ports - so be sure you really do want your logic blocks to be totally separate.   I think the docs say something about this too... Yep here it is. From http://www.altera.com/literature/hb/qts/qts_qii51008.pdf:   A design partition represents a portion of the design that you want to synthesize and fit incrementally. Incremental compilation maintains the hierarchical boundaries of design partitions, so you can use design partitions if you need to preserve hierarchical boundaries through the synthesis and fitting process. For example, if you are performing formal verification, you must use partitions with the full incremental compilation flow to ensure that no optimizations occur across specific design hierarchies. Beginning with the Quartus II software version 6.0, Altera recommends that you use Design Partition assignments instead of the Preserve Hierarchical Boundary logic option, which may be removed in future versions of the Quartus II software.

[Altera_Forum]

Yes, it works. Thanks Stevie.  

Thanks Samson anyway!!