Its not a big no-no, but its generally not necessary unless you're trying to do something very specific, eg., for a data path that goes from an FPGA to an off-chip device.
The Altera tools include a tool called the TimeQuest Timing Analyzer. Read the documentation for that tool.
An FPGA design consists of your HDL, the pin assignments for the design, and the timing constraints for the design.
Normally you would write your HDL so that it all uses rising-edges of the clock. However, after you have performed a timing analysis, it might be necessary to perform some "tricks" to meet timing at the FPGA I/O. One of those tricks is to invert the clock, another is to use a PLL to phase-shift the clock. The default trick of letting the FPGA synthesis tool program the I/O cell programmable delays is generally sufficient, so you should start by using that, i.e., use a rising-edge in all of your design and apply timing constraints, and see how you do.
Cheers,
Dave
