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Hi there,
I have a design that sends two LVDS signals (one data, one clock) off a cyclone 3 device. When the signal frequency was 250MHz or below, I can see those signals with a scope. But when the signal frequency increases to 276MHz, I don't see output anymore. What could go wrong here? Am I missing any settings here? HuaLink Copied
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If you are changing the frequency on the board without changing the frequency for your PLL or altlvds megafunction in Quartus, then you might be exceeding the range at which the PLL can lock with the setting produced during the compile. Recompile with the megafunction set to the same frequency as the board if you haven't already done that.
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Hi Brad,
Thank you for your reply. Actually I was changing it from the PLL.... But I think I know why now. The high frequency signal got attenuated too much at the frequency of 276 MHz. I guess with better impedance matching the problem may be gone. Thanks again. Hua
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