Flash Memory VHDL. Write Duration. JEDEC.

[Altera_Forum]

Hello, 

 I am using a flash memory amd29lv320d. It is CFI compliant. I designed a code for write, read and erase the flash in VHDL.  For read and erase I have what I expected (talking in terms of duration), but when I need to write it takes too long time.  For write 320000 bytes it takes more than 4 hours, but the datasheet says that the "Chip program time" is maximum 72 sec.  The reason is that the signal flash ready takes a long time to be asserted.  Does anybody have had some trouble similar?  Thank you.

[Altera_Forum]

Hello, 

 I decided to attach some image of the signals that I am generating from VHDL, maybe someone has already designed a driver for a Flash and can see something strange.  It is a standard FLASH, CFI jedec.  You can see the signal I_busy is the flag RY/BY that comes from the flash but takes too long time to be asserted.  Any sugerence will be apreciated.  Thank you.:cool:

[Altera_Forum]

Hello, 

 Just if somebody has the same trouble in the future.  I found the trouble. I had forgoten the pull up resistor in the RY/BY pin.  I used the pin assignment tool for add a weak pull up resistor .  Bye.