Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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bad chip name under quartus programmer

Altera_Forum
Honored Contributor II
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Hi All, 

 

I'm using a custom board with an EP3C10F256I7N device. 

When I configure the device using Quartus Programmer, the programmer detects the device but reports ep3c10/5 , instead of EP3C10F256I7N. However, the JTAG ID code is 0x20F10DD, which seems to be correct as this is the same in the EP3C10F256 BSDL file. 

JTAG configuration also goes fine, but my problem is that I use a Nios processor and when I try to download an ELF file, I got an error "Processor not responding". 

 

I suspect that it is due to the name mismatch. 

Anybody knows what EP3C10/5 is ? 

 

 

Please help.
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Altera_Forum
Honored Contributor II
460 Views

 

--- Quote Start ---  

Anybody knows what EP3C10/5 is ? 

--- Quote End ---  

 

 

 

I think it just means that the Programmer is saying the device it detected is either an EP3C10 or an EP3C5. I see the same thing for a Cyclone II device. My Nios processor runs fine, so I think the way the Programmer is labeling the detected device has nothing to do with your error.
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Altera_Forum
Honored Contributor II
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Make sure your quartus design is correct! Check reset and clock inputs in your design.

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Altera_Forum
Honored Contributor II
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Hi, 

 

Brad, Ketan many thanks for your support. 

 

Ketan you were right, my design was faulty. I forgot to properly managing reset for an Avalon component, thus stalling the Avalon bus. 

 

It now works perfectly. 

Thanks again. 

 

 

-- Cheers
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

... my design was faulty. I forgot to properly managing reset for an Avalon component, thus stalling the Avalon bus. 

--- Quote End ---  

 

 

 

In software version 8.0, the new System Console can help with debug of basic issues. It provides a method to do things ranging from checking whether a clock is running to doing Avalon reads and writes without using the Nios II processor. The System Console User Guide is available at http://www.altera.com/literature/lit-ug.jsp

 

 

From the User Guide: 

 

 

--- Quote Start ---  

The System Console performs low-level hardware debugging of SOPC Builder systems. The System Console provides read and write access to the IP cores instantiated in your SOPC Builder system. You can use the System Console for the initial bring-up of your printed circuit board and low-level testing. The System Console is the appropriate tool for all of the following tasks: 

 

  • Verifying that the clock is toggling 

  • Verifying component pinouts 

  • Testing memories and peripheral devices 

  • Determining the value of the reset signal 

 

--- Quote End ---  

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Altera_Forum
Honored Contributor II
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Thanks Brad, 

 

I'm aware about the new system-console tool, which IMO is a great tool. 

Unfortunaly, I tried using it, but with no success. Connection to JTAG master (NIOS CPU) could not be established because of Avalon stalling , I presume. 

 

However, I use system-console tool for other purposes, like ISP programming for an TI MSP430 microcontroller, see here : http://nioswiki.jot.com/wikihome/system%20console%20-%20msp430 

 

Great tool. 

 

--Cheers
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