Incremental Place and Route

[Altera_Forum]

Hello, I’m new in all of this so I need your help. The problem is the following: 

I’m working with Quartus II 7.2 and the device I’m using is a Cyclone II.    Well, suppose that I have a system A and I put it into the Cyclone, in order to test it I place a Sources and Probes block, called SP. If I see the chip planer (in Quartus) I see A in the corner of de FPGA. When I see the chip planner after adding the SP block A and SP are in the middle of the chip. So this, changes the skew of the signals in A and this is bad for me, very bad.    So I want the system A to stay in the original place after I add the SP. How can I do that?    I hope the explanation was clear.  So thanks for all.  Ignacio.

[Altera_Forum]

Hi, 

 I don't see your problem as that of incremental things. You can design without the need to spy on the fitter decisions at all. The fitter puts stuff as decided by the whole design so things migrate around. Give it freedom. If things are very bad you better see what is going in your design. Are you getting reported skew? then your clocking is to blame I am afraid...  kaz

[Altera_Forum]

Thanks Kaz… 

  I have 3 signal clock form a PLL, whose goes to a mux of 3.  I need that the skew of this signal be 0.  So when I implement the system with out SP (with out SP is the real system) I simulate it and I can calibrate the phase shift of the 3 signal with the PLL, hence, I can compensate the different delay of the mux, hence I can “set” the skew to 0.    So when I’ll test all system in the chip I need use a SP block, because I have 10 binary inputs and I haven’t 10 switches on the board. Using the SP block the fitter change all, hence, the initial calibration on the PLL is useless.     Kaz, can you explain the question please? Because I don’t understand  “Are you getting reported skew?”      My English is not good, so I hope you understand.     So thanks for all. Ignacio.

[Altera_Forum]

Hi, 

 you should avoid connecting the three clocks to a mux as you will be gating them and causing skew, though this can be done by experienced designers.  I am not clear what is your purpose of getting these three clocks. I thought you will use them for your design work to feed flipflops(registers). You can adjust the phase of each clock in the altpll instantiation(I think that is what you are doing), but this approach is complicated and nonrepeatable and it is better to use one clock for a safe design then control the rate through an enable signal.  By reported skew, I mean the compiler message tells you that there is skew.  kaz

[Altera_Forum]

Ok, I understand your idea. But we need the 3 signal clock because is the nucleus of the design, hence I need to know if is possible do the hierarchy compilation with the characteristic that I said in the first message. 

  Kaz, thanks, really thanks.  Ignacio

[Altera_Forum]

Hi, 

 In that case you can use logiclock or incremental compilation(bottom-up). There is a lot of info on altera site including a very good video demo.Just make a search for incremental compilation on this site  kaz

[Altera_Forum]

--- Quote Start ---  Ok, I understand your idea. But we need the 3 signal clock because is the nucleus of the design, hence I need to know if is possible do the hierarchy compilation with the characteristic that I said in the first message.    Kaz, thanks, really thanks.  Ignacio  --- Quote End ---    Hi Ignacio,  what are you doing with your SP Block ? Where is the block located in your design ? Which Timing Analyzer did you use and how do you constrain the clock signals ?

[Altera_Forum]

I think you want to look at Timing Constraints, specifically TimeQuest. Once you enter timing constraints, the fitter than works to meet those constraints(although in general, there isn't a straightofrward skew constraint). If data comes in and feeds a register clocked by these three clocks, then doing set_input_delay constraints on the input will constrain the datapath in relation to each clock. 

Note that it's impossible to have 0ns skew, no matter what technology you have. I'm guessing you want it "as tight as possible". A PLL whose output feeds globals(which it has to) will have very good skew. Probably a hundred picoseconds or so, but timing analysis will tell you more. Once you go to a clock mux out of logic, your skew will jump considerably with careful design, and could get horrible without hand-crafting(i.e. one clock might go through two levels of logic while other clocks only go through one, resulting in a ns of skew). I would look at using the altclkctrl megafunction, although I don't remember if it can mux 3 clocks or only 2. If you can use that, it will get you back to the ideal case.

[Altera_Forum]

--- Quote Start ---  I think you want to look at Timing Constraints, specifically TimeQuest. Once you enter timing constraints, the fitter than works to meet those constraints(although in general, there isn't a straightofrward skew constraint). If data comes in and feeds a register clocked by these three clocks, then doing set_input_delay constraints on the input will constrain the datapath in relation to each clock. Note that it's impossible to have 0ns skew, no matter what technology you have. I'm guessing you want it "as tight as possible". A PLL whose output feeds globals(which it has to) will have very good skew. Probably a hundred picoseconds or so, but timing analysis will tell you more. Once you go to a clock mux out of logic, your skew will jump considerably with careful design, and could get horrible without hand-crafting(i.e. one clock might go through two levels of logic while other clocks only go through one, resulting in a ns of skew). I would look at using the altclkctrl megafunction, although I don't remember if it can mux 3 clocks or only 2. If you can use that, it will get you back to the ideal case.  --- Quote End ---    The altclkcrtl megafunction supports up to 4 inputs. Unfortunately only two could be driven by a pll. It is also not possible to cascade altclkctrl blocks. In my point of view they can not be used here. Maybe somebody has an idea ?

[Altera_Forum]

If you really need 3, then you're correct. Another thought is that, depending on the family, PLL's are reconfigurable, so you could reconfigure one of the outputs. This won't allow "instantaneous" change, but might work.  

You might want to post what you're doing here for other's input. I have seen designs that absolutely do require clock muxes, but I have seen many cases where users start doing this when there is a much better solution. Also, where does the 0ns(or whatever it is) skew requirement come from?

[Altera_Forum]

Well!! Firth of all, I’m sorry I couldn’t replay all the post for two reasons: 1) I didn’t have time and 2) the PC has a little problem. 

  Kas: Very thanks, finally I went to the Altera’s page and I found “incremental compilation” I saw a video that explained the problem. The real name of my problem is “Logic lock”    Pletz:  Thanks for your questions.   “What are you doing with your SP Block?”  So when I’ll test all system in the chip I need use a SP block, because I have 10 binary inputs and I haven’t 10 switches on the board.    “Where is the block located in your design?”  In the middle of the chip, more or less.   ”Which Timing Analyzer did you use and how do you constrain the clock signals?”  Which? I’m sorry; I don’t understand your question.  I can’t constrain the “clock signals” because when the diferents signals thought the mux of 3 those lose the properties of a signal clock and takes the properties of a common signal. If I don’t wrong the “Timing Analyzer” only function work with cloc signals.    Rysc:  Thank for your advice  I agree with you, but I believe that the “Timing constraints” is only applicable to the clock signal, and my problem is inside mux, and the signals are common, not clocks. I mean the input signal of the mux are clocks but inside are not.  In Clycone II is not possible connect more than 1 output PLL to an “altclkctrl”. If, I don’t remember wrong, the manual of the “altclkctrl megafunction“said this. So this is the reason to use a simple mux of common signal.   Is probably that is not a great idea (use the mux) but for the moment is necessary pass this process to learn.      I'm really grateful for the patience and friendly treatment your have given me.  Really, really thanks.      Ignacio.

[Altera_Forum]

Timing Constraints are considered the way to go, because a) they guide the fitter in it's choices and b) they give clear feedback on whether constraints were made or not. Just because some logic was placed close to some other logic, you still have no idea if it really met timing. 

What skew can you handle? I haven't seen that posted, and it could make a huge difference. Also, what are the clock rates? If this is something where you can physically control with signals and probes, then it's probably slow enough that it doesn't matter. Since that uses the JTAG port, it clocks the data in serially and then does one clock to do a parallel transfer(I haven't looked at it, but assume this is the way it works), which is mighty slow. And you can constrain your clocks as so: Look at the middle example of: http://www.altera.com/support/examples/timequest/exm-tq-clock-mux.html Just make it 3 clocks. Of course, if you're just switching between asynchronous clocks you will have clock glitches. That's one of the major reasons everyone is so against this. If you can, either disable all the logic while switching(perhaps have a clock enable).

[Altera_Forum]

Rysc:  

Thanks, I’m reading this information.    bye Ignacio

[Altera_Forum]

--- Quote Start ---  Rysc:   Thanks, I’m reading this information.    bye Ignacio  --- Quote End ---    Hi Ignacio,  maybe now I got what you are doing with the SP-Block. You have in your design some inputs dangling and you are stimulating these inputs with the SP-Block ??? What is the purpose of this input, when you have no input signal for them ? But why do you have a skew problem with the clock ? You always use only one clock at time, so where is the problem. Of course have to constraint them like Rysc described in his post.

[Altera_Forum]

Hi Pletz 

  The purpose of the block SP is connect the design with a PC, because I have 10 binary inputs and I haven’t 10 switches on the board.    Yes, I only use one clock at time, but the output needs that the skew of this signal be almost 0.    Thanks Pletz  Ignacio

[Altera_Forum]

--- Quote Start ---  Hi Pletz    The purpose of the block SP is connect the design with a PC, because I have 10 binary inputs and I haven’t 10 switches on the board.    Yes, I only use one clock at time, but the output needs that the skew of this signal be almost 0.    Thanks Pletz  Ignacio  --- Quote End ---    Hi Ignacio,  I don't know your design, but when I assume that your design uses one clock at time and is synchronous, you only could have a problem in your input ( setup times) or output ( clock to output) timing. Why do you need a skew of almost 0 ? Is it a requirement of the input or output timing ?  Kind regards  GPK

[Altera_Forum]

Hi Pletz, 

  The problem is in the output signal, because it use one of the clock at time, and this clock is select for the inputs. So in the output you can see the deferens between the clocks, hence if this deferens are different that I want, so is wrong.     I hope the explanation was clear.    Thanks Pletz    Ignacio.

[Altera_Forum]

--- Quote Start ---  Hi Pletz,    The problem is in the output signal, because it use one of the clock at time, and this clock is select for the inputs. So in the output you can see the deferens between the clocks, hence if this deferens are different that I want, so is wrong.     I hope the explanation was clear.    Thanks Pletz    Ignacio.  --- Quote End ---    Hi Ignacio,  I don't get want mean. Is it possible to post a small drawing of your design to get an overview. Sorry that I'm not able to get it without it.  Kind regards  GPK

[Altera_Forum]

Hi Pletz I'm sorry. I was searching the authors of the paper that I used but they don’t answer my mails. My idea was give you this paper so you can understand the problem perfectly.  

If they respond me I’ll tell you.  Merry Christmas and Happy New Year.  Thank you Adios Ignacio.

[Altera_Forum]

Hi everyone, I have an answer for the authors of the paper and you can see it in: 

http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4712525&arnumber=4663501&count=59&index=51    Thanks Sr Angel de Castro    Adios. Ignacio.

[Altera_Forum]

--- Quote Start ---  Hi everyone, I have an answer for the authors of the paper and you can see it in:  http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4712525&arnumber=4663501&count=59&index=51    Thanks Sr Angel de Castro    Adios. Ignacio.  --- Quote End ---    Hi Ignacio,  unfortunately I have no access to the document without buying it. What I could see in the summary was that they used a XILINX FPGA which includes a DLL. It looks tome that they used the DLL in there design.