Error message during the compilation

[Altera_Forum]

Hello, 

 I'm working with DSP Builder and Quartus II since few weeks, so I don't have much experience concerning troubleshooting.   When I try to compile a model (created with DSP Builder Blockset) in simulink environment using "DSP Builder - Signal Compiler", I recieve following error message:  Out of memory in module quartus_map.exe (2138 megabytes used)  Error during Compilation: Synthesis failed.     Does anyone have experience with such an error?

[Altera_Forum]

In Quartus release notes, you'll find the minimum PC memory requirements for synthesis of a particular FPGA device project. I guess, you need some extra RAM.

[Altera_Forum]

Are you any other error message except this one?

[Altera_Forum]

I forgot to mention, that as a first step you should try to close all other, partcularly memory consuming applications.

[Altera_Forum]

I don't think closing other programs will help (unless your system has non-standard virtual memory settings). 

 If you're on a 32-bit Windows platform, you're running into the fundamental limit of VM that can be allocated to a single process. 32-bit Linux will allow a process to allocate ~3GB of VM address space. 32-bit executables on 64-bit OSs gives you the full 4GB (2^32). If you need more than that, you need to run 64-bit executables.  - Mark

[Altera_Forum]

--- Quote Start ---  I forgot to mention, that as a first step you should try to close all other, partcularly memory consuming applications.  --- Quote End ---     - There are no error messages except this one. - Another programms are closed. - It's a 32 Bit Windows platform with 2 GB RAM and 3 GB virtual memory.

[Altera_Forum]

--- Quote Start ---  I don't think closing other programs will help (unless your system has non-standard virtual memory settings).  --- Quote End ---   I experienced just this with a Win2k notebook.

[Altera_Forum]

What part are you targeting? 

 Can you look at the End of Synthesis rreport and see how many FPGA resources are being "authored" by the Matlab tool, and then Synthesized?  Try running Signal Compiler in Advanced mode (see the tab?), then just build the project, then create the design files.  Then launch Quartus and open the project and just run Synthesis and see how many resources are being asked for?  Maybe you are blowing out of the top of the targeted part?  ------ Or maybe you are targeting to large of a part?  --------  You may need to look into doing some bit trimming along the way in your DSP design to reduce the needed resources, while still keeping the desired design intent. That is the beauty of modeling before compiling.

[Altera_Forum]

--- Quote Start ---  What part are you targeting?   Can you look at the End of Synthesis rreport and see how many FPGA resources are being "authored" by the Matlab tool, and then Synthesized?   Try running Signal Compiler in Advanced mode (see the tab?), then just builed the project, then create the design files.   Then launch Quartus and open the project and just run Synthesis and see how many resources are being asked for?   --- Quote End ---     - I'm trying to compile the algorithms for the Device EP3C40F484C7 with 39,600 LE.   What do You mean with "create the design files"?  In Advanced Mode of Signal Compiler it is possibe to create the project, but not to run the Synthesis. The same error message (as in the Simple Mode by trying to compile) appears by trying this.   When I remove some parts from the project (which can be compiled separately), the project can be compiled. For the reduced project 20,423 LE are required.   Now, I will try to simplify some functions.

[Altera_Forum]

After the reducing and optimizing the algorithms, the project can be compiled but there are now two error messages during the Fitting with the Signal Compiler: 

 Error: Design contains 48306 blocks of type combinational node. However, device contains only 39600. Error: Can't fit design in device      The project still seems to be too big for the Device EP3C40F484C7.  The required number of LE is 48,549. This is shown in the Compilation Report after Synthesis process in Quartus II.

[Altera_Forum]

OK, so it looks like you are on your way to unerstanding that choices made in the Simulink model will effect the "amount" of both logic and memory needs of the end HDL design. 

 The challenge now is to figure out what is sensitive to what.  Think about how your control items may be effecting your logic structures. Think about the width of data paths, and how it will propogate through to either Flip flop generation or memory needs.  If you have a 10 x 10 function, you will need 20 bits to store the result. Do you need to keep all 20 bits across the design (maybe resulting in 20 registers, times multiple ranks as it gets clocked through the design), or can you trim off some of the lower order bits? (At what cost to the quality of the end result?) (Simulation is good)  It will take a little playing about and tugging here and there to get a feel for how much of what is created by this or that structure.  Maybe use the RTL viewer to "see" what is getting generateed (as a way to pull back the layers of the code being generated).  You are heading in the right direction.