PCB design and pin assignment

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

PCB design and pin assignment

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Hello

I want to design a PCB with a Cyclone III FPGA. The device will be a BGA with around 350 IO pins. I already read an application note (AN114) about escape routing but there is still a principal question for me:

I would like to make pcb as easy as possible and just route the IO-pins successively as I escape from the FPGA to an IO-driver or connector. So I would not check on what bank an IO-pin relates.

Does this approach have a negative impact on the logic cells that will be used?

Is there a reference design or guideline available regarding placement and use of capacitors, does and don'ts?

Thank you very much for your help

Geri

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