synchronize pll

[Altera_Forum]

On CycloneII, is it possible to re-synchronize or start a pll on an async event such as a pulse? 

 I have a 50Mhz pll clocked state machine that is triggered from a single external async pulse. I also have a Flash A/D that is running on a separate, continous 10mhz pll clock. What I would like to do is synchronize the two plls such that the A/D clock is aligned to my external pulse so its sampling times are predictably synched to my state machine logic.  The A/D is designed to operate from a continuous clock only and has an internal 4clk conversion delay. The very first result may be bad but I can live with that. I thought of using counters to generate a 10Mhz clock directly from the 50Mhz state machine logic but it would be better if I could use a pll so as to have some control over phase.

[Altera_Forum]

Look at: 

http://www.alteraforum.com/forum/showthread.php?t=1473&highlight=pll  This is a sample design I did to have PLLs across multiple FPGAs correlate. I think it might work for what you're doing. (You don't need most of the design, but the idea of using the altclkctrl as a enable is the trick...)

[Altera_Forum]

I think, the only suitable solution to synchronize a clock to single pulse is a digital PLL created in your design. But the timing resolution is limited by the reference clock, could be up to 300 or 400 MHz with cyclone II.

[Altera_Forum]

Where is the pulse coming from that would start your state machine? How do you intend to phase align your 50 MHz clock with the 10MHz clock that the A/D is using?

[Altera_Forum]

It is from external equipment. This trigger pulse is latched by 50Mhz logic. After latching, the very next clock starts the state machine. I will probably use the digital pll method suggested, or just generate the 10Mhz clock from the 50mhz logic. Counters are simple.

[Altera_Forum]

Yes, starting a :5 clockdivider on the start pulse would be the most simple solution. (In case of a single start pulse, a digital PLL can't do anything more). As an disadadvantage, the clock divider output has more jitter than an analog PLL output. This would be a problem only in applications, where a input waveform has to be reconstructed from samples, e. g. digital receivers or FFT processing of input data, where the aperture jitter is converted in an amplitude uncertainty respectively additional noise. Also the clock output delay has to be considered when defining the ADC data read timing. Processing of AD data should be performed in the 50 MHz domain with a 10 MHz clock enable.

[Altera_Forum]

The DDIO megafunction could be used along with a small state machine to generate a 10MHz clock off the 50MHz clock. tco of the DDIO is very small and an indicator of the rising edge of the 10MHz generated clock could be used in the 50MHz domain. This would allow the 50Mhz domain to know the phase of the 10MHz domain generated by the DDIO. All logic would stay in the 50Mhz domain.

[Altera_Forum]

Depending on the used ADC, it may be operational also with 40 or 60% duty cycle clock, so the somewhat more complex DDIO solution won't be necessary. Another point is, that the ADC may have a startup time after applying the clock and possibly show a transitional reaction after shifting the clock phase.

[Altera_Forum]

This A/D does need close to 50% duty, so some of the circuit options won't work. The odd divider needs both pos and neg edge switching as the DDIO would use. I don't see any cyclone primitives with negative clocks so I wonder how they do that one and still be symmetrical. I'll try it if I can figure out how. 

 A clock doubler using a delay line primitive would simplify things but I don't see that either.

[Altera_Forum]

DDIO configured as a single bit output. Write a small state machine to send 1's to datain_h and datain_l for two 50 MHz cycles. Then send datain_h a '1' and datain_l a '0' on the next 50MHz cycle. For the final two 50MHz cycles, send datain_h and datain_l zeros. Just repeat this and you have a pretty good 10MHz clock based on the 50MHz clock. Constrain the DDIO output with tco and tco_min(or is it min_tco). This method would allow you to not run the 10MHz DDIO clock until you see the pulse telling you to do the A/D conversions, thus avoid having to wait for then next rising edge of a free running 10MHz clock. 

 Add in a signal that lets your control logic(running in the 50MHz domain) know when the rising edge of the 10MHz DDIO clcok happens and you can control the A/D in the 50Mhz domain and still run the A/D at 10Mhz.  I do not think this is a complex solution, it is just sound synchronous design to achieve the requirements. Only you know what your requirements are so you'll have to choose the best solution.

[Altera_Forum]

How would you get this functionality if you had to write the verilog? It seems you can't just say @(posedge clk or negedge clk). You'd have to have one clause for each edge and interleave them - but how?

[Altera_Forum]

Check out http://www.altera.com/literature/ug/ug_altddio.pdf

[Altera_Forum]

I wrote up some verilog for this (12ff,3gates) and the functional simulation looks perfect, but the timing simulation does not show correct values for one of my shift registers. I see in the altddio doc that there are special ddr register cells, and special sim libs also. I'd prefer to stick with my own code, but without knowing how to specify those special options I guess I will have to use the megafunction.

[Altera_Forum]

The Quartus Handbook clarifies that DDIO can't be inferred from HDL code: 

  --- Quote Start ---  You must instantiate megafunctions to target certain device and high-speed features such as LVDS drivers, PLLs, transceivers, and double-data rate input/output (DDIO) circuitry.  --- Quote End ---   Other solutions that combine posedge and negedge clocked registers are possible, but you have to take care not to generate glitches. One option is to use a asynchronous clear from a register clocked at the opposite edge. See: http://www.edaboard.com/viewtopic.php?t=303735

[Altera_Forum]

This short code works pretty well. Functional sim looks perfect but timing sim does not init properly. On CII grade8, a 50mhz:10mhz conversion has 50% duty. I don't see glitches, but it does not always start aligned to the 1st rising edge like I want. Could be improved. 

   --- Quote Start ---  module ddrdiv5_clk ( clk50, nReset, cnt_en, clk10_out );  input clk50; input nReset; input cnt_en; output clk10_out;  reg[4:0] ddsrh; reg[4:0] ddsrl; reg first;  assign clk10_out = ddsrh[0] & (ddsrl[0] | ~ddsrh[4] | ~ddsrl[4]);  always @(posedge clk50 or negedge nReset) begin  if(!nReset)  begin  ddsrh[4:0] <= 5'b01110;  first <= 1'b0;  end  else  begin  if(cnt_en)  begin  ddsrh[4:0] <= {ddsrh[0],ddsrh[4:1]};  first <= 1'b1;  end  else  begin  ddsrh[4:0] <= ddsrh[4:0];  end  end end  always @(negedge clk50) begin  if(!first)  begin  ddsrl[4:0] <= 5'b00110;  end  else  begin  if(cnt_en)  begin  ddsrl[4:0] <= {ddsrl[0],ddsrl[4:1]};  end  else  begin  ddsrl[4:0] <= ddsrl[4:0];  end  end end  endmodule  --- Quote End ---