PLL input from non-dedicated clock pin

[Altera_Forum]

Hello all, 

 I've struck with a simple problem and I'm almost nearing the wall in terms of options.  I've a design in which the clock is coming from a non-dedicated clock pin (PIN_AJ16). I've to generate a divide-by-2 clock and I read in the forum the best way is to use PLL.  PLL can be driven from Global clock lines or dedicated clock pins. So, I instantiated a ALTCLKCTRL megafunction to route the pin on global clock line and then use that as input for the PLL. But, I still get the same error  Error: Can't place Top/Bottom or Left/Right PLL "sclkpll:u7|altpll:altpll_component|sclkpll_altpll:auto_generated|pll1" -- I/O pin ClkIn (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device  Here is the code for the same  sclkctrl u1 ( .inclk(ClkIn), .outclk(ClktoPLL)); sclkpll u2 ( .inclk0(ClktoPLL), .c0(ClkfromPLL));   Its almost like the ALTCLKCTRL block has been removed by optimization. Can you suggest any alternatives?  Thanks, Gopal

[Altera_Forum]

What device? Some of the older architectures didn't allow this type of layout.  

If you're divide by 2 clock is the main clock, it may not be a big deal. The problem with gated clocks is that they have skew compared to the non-gated clocks, and so transferring data back and forth is difficult. That being said, it can be done. (What you're trying is the best option, but there are plenty of designs with gated clocks like this). The other option is to take the divide-by-2 output and have it feed the clock enable of the register and have the clock port fed by the main clock. This disables the clock on every other cycle, and makes a divide-by-2 domain that is not skewed from the main clock domain. (In reality, everything is fed by the main clock domain). That is just as good as using a PLL, and sometimes better, since no PLL is required, no locking, no use of two clock trees, etc.

[Altera_Forum]

from: http://www.altera.com/literature/hb/cyc3/cyc3_ciii51006.pdf 

   --- Quote Start ---  (3) This input port is fed by a pin-driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another PLL or a pin-driven dedicated GCLK. An internally generated global signal cannot drive the PLL.  --- Quote End ---  

[Altera_Forum]

I'm using Stratix III device. I didn't see any restriction on the logic driving the GCLK line (which can feed a PLL). 

 There are clock muxes (2:1) in the design with each clock being gated before it is fed to the mux. I saw the clock gating is not being turned into register enable. So, I will have to generate the divide-by-2 clock.  Thanks, Gopal

[Altera_Forum]

--- Quote Start ---  I'm using Stratix III device. I didn't see any restriction on the logic driving the GCLK line (which can feed a PLL).  --- Quote End ---    I think that actually, no Altera FPGA family allows this. PLLs can't be driven (directly or indirectly) from a general purpose I/O pin.  Newer families allow the PLL to be driven from a clock control block, but only when the clock control block is driven by a dedicate clock pin, or by the output of another PLL.  As the quote above from the CIII handook, internally generated signals can't drive a PLL. But it is even worst (that handbook is not complete), general purpose I/O pins can't drive PLLs either. This is missing in the CIII handbook, but it is mentioned in other ones (at least I can see it in the SIV handbook).  In other words, you are correct that there is no restriction to drive the GCLK, but this is true only as long as you don't try to drive a PLL from it.

[Altera_Forum]

Sorry, I take it back. I missed this in the Stratix III manual 

 Stratix III device PLLs cannot be driven by internally generated GCLKs or RCLKs. The input clock to the PLL must come from dedicated clock input pins/PLL-fed GCLKs or RCLKs only.  So, I'm left with using a logic divider for the clock.

[Altera_Forum]

As far as you described the problem, I don't think that using a PLL for the clock divider would bring an actual benefit. PLL is mandatory, if e.g. generating multiple clocks with well defined phase relation.

[Altera_Forum]

Suppose I've to transfer data from clk domain to clk/2 then PLL can help reduce the skew on the clk/2, right? 

 I've added create_clock and create_generated_clock statements in the SDC file. I see sometimes wrong data being latched in clk/2 domain. I hope Quartus will automatically take care of the hold time violation due to clock skew. I will analyze it a bit further.

[Altera_Forum]

Do you actually need to use clk/2 as a clock in your design? Won't a clock enable work as well? With the "ripple" clock, even if Quartus will be able to achieve timing closure, you considerably restrict the fitter in achieving optimal timing in other parts of the design and at least increase synthesis effort.

[Altera_Forum]

I've added a picture to visualize the problem. 

 For the sake of discussion module A is a block-box and the logic cannot be altered. TimeQuest reports max frequency of Mux_Clk to be 80MHz. So, I've the following options.  1. Run Clk2 through a divider and feed to Module A.  2. Gate Clk2 before feeding Module A and Quartus will convert it to register enable. I'm assuming Quartus will merge "En2" and the new enable for frequency division. I will also have to give multi-cycle constraint in SDC, correct?  I've one more question. How to know the individual max frequency for each of the modules? Suppose the critical path is in module B and I know I won't be using it, then theoritically I can set Clk2 to the max supported by A or C. But TimeQuest will report only for the top level clocks.  -Gopal

[Altera_Forum]

--- Quote Start ---  Suppose I've to transfer data from clk domain to clk/2 then PLL can help reduce the skew on the clk/2, right?  --- Quote End ---    That is correct.    --- Quote Start ---  I've added a picture to visualize the problem.  --- Quote End ---    The picture doesn't match your description. According to the picture, you are not dividing by 2. And what is more important, you are muxing between two clocks, which is quite a different issue. So please let us know exactly what you want to do.

[Altera_Forum]

I've to run module A at half of the Clk2 frequency. I've not depicted the divider because I'm not sure which is the best way to go about 

 1. Ripple clock divider 2. Gate the Clk2 before module A (Now there will be 2 enables, one outside module A, one is already inside, I hope it will not be an issue)  I've already tried 1 (saw some hold slack issues) and will give 2 a shot.