Dear all,
I am a newbie in this FPGA task field (or maybe it is more appropriate to say in embedded system design field). So please kindly to help me :)
Here is the case :
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Currently I got tasks about interface design on Nios-II. One of the task is to connect a stratix IV fpga with a DSP board via HSMC connector which controlled by the Nios-II. The DSP board will transmit several streaming data parallelly. For example, there are 5 streaming data that will be transmitted parallelly. For each streaming data, it consists of 10 sub-data and one sub-data consists of 12 bits.
*Actually there is also various data rate specifications, but for now lets ignore the data rate specification issues. :D
So here are my questions :
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1. To implement driver for case above, I thought I only need a DMA (or SG-DMA) and a PIO (of course with correspond memory & Nios connections). Is it correct?
2. In my task, the parallel data transmission is controlled by a clock signal and synchronization signal which are sent by DSP board. I've tried to design the driver using Altera's available peripherals (I used a SG-DMA and a PIO) but I got confused how to include these two signals (clk and synch) in my design. Does it mean I have to make a new component to implement this driver?
That's all for now. I'm looking forward any advices. Thank you guys!
