Looping error

[Altera_Forum]

this is typical counter description, 

but how there's this error when i try to compile it in quartus    --- Quote Start ---  Error (10500): VHDL syntax error at count31.vhd(31) near text "intern_value"; expecting ";", or "for"  --- Quote End ---    I can't imagine any errors ther     --- Quote Start ---   LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL; entity COUNT31 is   port ( CLK: in std_logic;   COUNT: out integer);   end COUNT31;  architecture behav_COUNT of COUNT31 is  begin   P_COUNT: process   variable intern_value: integer :=0;   begin   COUNT <= intern_value;   loop   wait until CLK='1'   intern_value:=(intern_value + 1) mod 32;   COUNT <= intern_value;   end loop;  end process P_COUNT;  end behav_COUNT;  --- Quote End ---  

[Altera_Forum]

expecting ";" means in most cases just this: a ";" is missing (usually in the previous line).  

 After correcting the simple syntax error, the compiler sees that the code isn't synthesizable at all, cause it has an endless loop. I also don't understand what is intended here.

[Altera_Forum]

Yes, this is far from a typical counter: 

1) Don't use variables unless you absolutely have to, or absolutely know what you are doing. 99% of code doesn't need them and gets along better without them. (This one is debatable, but I've seen users have far too many problems. Anyway, make that a signal. 2) Don't make it an integer. Integers are defined over an enormous range, when all you want is 5 bits to count to 31. Basically you're making synthesis create a huge structure and rip it down. In this small example it will work, but done over and over makes your code slow. It also opens you up to mistakes where you do a typing error, and suddenly synthesis takes forever because your 5 bit counter is now 32 bits(or whatever the native length of integer is, I forget). Use integer only for things like indices of a loop. So this should probably be std_logic_vector(4 downto 0);, or if you use integer, put a well-defined range onto it. 3) Don't use loops. Again, you can run into infinity like you're doing here. Use a for statement if you must, which is well defined, and in this case don't use either. 4) Have an asynchronous reset. I won't get into it here, but good practice to get into. 5) Don't use a mod unless you're doing math. This is just a counter, c <= c + 1. If you want it to reset early, just check if it is at the value you want to reset at.  6) In Quartus VHDL, go to Edit -> Insert Template -> VHDL -> Full Design -> Arithmetic -> Counter, and then insert the one you want into a blank page. Then make sure you understand everything about this. I don't mean to pick on the code, but there are just a lot of things that can go wrong with how you're doing it. Make sure you get a at least one VHDL book and start pouring through the examples, and mimic them in your code. (Or search on the web). Good luck.

[Altera_Forum]

Well, actually that was an example from a book. That's what frustrates me. I'm experimenting the loop statement. 

 Actually, I'm writing a data acquisition for a camera. I'll try the examples first. I'll update this thread as often as possible.  Thanks for the prompt reply.

[Altera_Forum]

Well I'll just put my foot in my mouth.

[Altera_Forum]

Here's the scenario, typical camera have vsync,href,pclk and 8-bits data. 

vsync represents new frame href represents new line pclk represents new pixel http://img85.imageshack.us/img85/3275/outputsignalue4.jpg  I would like to capture the first 50x50 pixels of the frame and another frame after the 60th frame.  All I need is two frames.  I'm getting this error   --- Quote Start ---  Error (10519): VHDL Type or Variable Declaration error at camera.vhd(44): bounds of type or variable range must have same type  --- Quote End ---      --- Quote Start ---  Error (10515): VHDL type mismatch error at camera.vhd(44): integer type does not match string literal  --- Quote End ---    Here my code:   --- Quote Start ---  LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;  ENTITY camera IS   PORT  (  start : IN STD_LOGIC;  pixel : IN STD_LOGIC_VECTOR(7 DOWNTO 0);  clk : IN STD_LOGIC;  vsync : IN STD_LOGIC;  href : IN STD_LOGIC;  pclk : IN STD_LOGIC;    pixel_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);  reference : OUT STD_LOGIC  );   END camera;  ARCHITECTURE behave OF camera IS  SIGNAL frame_count : STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL line_count : STD_LOGIC_VECTOR(6 DOWNTO 0); SIGNAL pixel_count : STD_LOGIC_VECTOR(6 DOWNTO 0);  BEGIN     PROCESS (vsync, href, pclk)  BEGIN    IF start='1' THEN--------------------------------------------STARTS THE CAPTURING SEQUENCE    frame_count <= (OTHERS => '0');  line_count <= (OTHERS => '0');  pixel_count <= (OTHERS => '0');    IF(vsync'EVENT AND vsync = '1' ) THEN  FOR frame_count IN "0000000" TO "111100" LOOP  frame_count <= frame_count + "0000001"; -------------COUNTS FRAME UNTIL 60    IF(href'EVENT AND href = '1' ) THEN  FOR line_count IN "0000000" TO "110010" LOOP  line_count <= line_count + "0000001";---------COUNTS LINE UNTIL 50    IF(pclk'EVENT AND pclk = '1' ) THEN  FOR pixel_count IN "0000000" TO "110010" LOOP  pixel_count <= pixel_count + "0000001"; --COUNTS PIXEL UNTIL 50    pixel_out<=pixel;-----------------------------OUTPUTS THE PIXEL DATA  reference<='1';------------------------------FOR SAVING THE DATA INTO RAM PURPOSES  END LOOP;   END IF;  END LOOP;  END IF;  END LOOP;  END IF;  ELSE    null;  END IF;     END PROCESS;   END behave;   --- Quote End ---  

[Altera_Forum]

I don't try to comment all obvious design problems. Just two points: 

 1. You should think of a process as code, that is executed always (in case of combinational code) or for each clock event (in case of clock synchronous process). In synthesizable code, you can't stop a process and wait for an event or schedule of a delay.   2. A loop is a method to create parallel structures, but not a sequence in time. All iterations are executed simultaneously.  A typical FPGA solution for the presented problem would use a system clock and synchronize all external signals to this clock. Also an external signal, most likely the pixel clock could be used as clock. If the other signals have defined timing related to pixel clock, the could be used as clock qualifiers, but synchronizing them would create a better defined timing.   As a consequence, hsync and vsync would not be processed as independant clocks rather than by synchronous edge detection.