About PLL output to driver DAC from top to bottom

[Altera_Forum]

A DAC chip on board needs clock but this DAC located near FPGA bottom. 

Now I conter the problem: how to design a clock network that driver the DAC from the PLL output pin of the chip, while the main base clock is located top of the chip, which means the this clock signalrouter cross the whole FPGA chip(from top to bottom), any good idea or better solutions?

[Altera_Forum]

I guess, the data outputs are also near the DAC? Generally, it can't be avoided in many designs to route clocks and other fast signals "crisscross" the logic array. This may cause additional effort for place&route tools, but is succesful in most cases. At worst, you can precompensate a systematical routing delay through PLL phase shift.

[Altera_Forum]

Thanks FvM, ur right,data outputs are also near the DAC.  

The the pic follow will tells what I posted. Only one clock input from the TOP of FPGA, and the DAC near the bottom need a clock, how to design this clk by using PLL of FPGA? http://f18.yahoofs.com/users/47d1f3bdz49e62bdd/2bdc/__sr_/e30e.jpg?phI9i0HB70MSwrxz

[Altera_Forum]

Hello, 

 the file at yahoo ist accessible to me. General it's not said, that you need a PLL or a dedicated clock output for the DAC clock. It depends on the clock speed. I think, up to 100 MHz should work with normal routing in most cases. The PLL options are availabel dependant on FPGA family. E.g. with Cyclone III, PLL's can be chained and also driven from gloabal clock resources, you can drive a PLL at the bottom from clock input at the top, either directly or through a PLL. With Cyclone II, PLL input is limited to regional clock pins.  On first try, I would connect the DAC without special measures, using the default global clock resources. Quartus will complain about using a non-dedicated clock output, but that's just a warning. You can check timing, it may be already o.k. For higher speeds, fast output registers can be used (depending on design structure, they may have been used without explicite definition). Fast output registers and the same pin routed to a pin can already give suitable timing, but hold time may be too short. You can specify a small amount of output register delay then (< 1 ns) or use different clock phases for clocking the output registers and clock output.  Regards, Frank

[Altera_Forum]

Thanks FvM, the pic URL as: 

http://photos.i.cn.yahoo.com/04400327037/2bdc/e30e.jpg/ (http://photos.i.cn.yahoo.com/04400327037/2bdc/e30e.jpg/)  I hope this time will work:-).  Regards markman