Usage of PLL output pins

[Altera_Forum]

In Cyclone-III EP3C16, there are 4 PLLs. I only need to use 2 of them. Each PLL has one dedicated physical output pin. In my application, I need 2 or 3 physical outputs from one PLL. I think that I could use the output pins of those 2 unused PLLs and connect 1 or 2 outputs of the used PLL output to them through GCLKs then to outside of the FPGA. Would it be possible for somebody to confirm this? Many thanks.

[Altera_Forum]

There is only one dedicated output pin that is directly driven by the PLL. A PLL can drive other I/O, but most drive a global to get to these I/O. The global adds a little jitter/noise to the clock output. 

That being said, I've never seen using regular I/O as a problem. I've seen people drive clocks off regular I/O and run 200-300MHz interfaces quite easily. What are you doing with your clocks? Personally, I think using regular I/O is almost always good enough(I've never seen a case where it wasn't) and that the dedicated outptus tend to just throw users off thinking they have to use it.

[Altera_Forum]

I agree with Rysc. Regarding your question, usually what I do when I have a question like yours is just perform a simple test compilation in Quartus. Make a simple dummy project and drive the clock outputs to the four output pins of your choosing. Quartus will tell you if you've done something wrong. 

 Most likely you'll get a warning regarding jitter performance on any clocks that use a global route rather than a dedicated clock output path. And going by Rysc's experience (which I would trust above my own) you could ignore this.  Jake

[Altera_Forum]

If you drive the the clock out using a DDROUT primitive, the jitter warning will disappear.