Viewing Design files from Example folder (Cyclone III dev. kit)

[Altera_Forum]

Hello,  

 I have been trying to develop some form of memory controller to use the SSRAM chip supplied with my Cyclone III starter board. It was suggested that I view some examples provided in the CIII_Starter_Kit_v.7.2 package which I found online. In the example project named QB3_Control_Panel there are a number of blocks which are presumably programmed using a hardware description language. When I attempt to view the design file for these blocks the file is displayed in symbols that I do not understand. Is there a way for me to view these design files in VHDL, or any other HDL? Thanks.   Andre

[Altera_Forum]

Some IP is encrypted(which makes most text editors display it as undecipherable symbols), which would explain what you're seeing.

[Altera_Forum]

Thanks, I kinda figured, I was just hoping there was a way around this to bypass the encryption.  

 Andre

[Altera_Forum]

Encrypting design files for rather trivial functions as the said SSRAMController.v is actually annoying. Apparently this isn't Altera politics but related to the Terasic ownership of some components. Altera supplies most design files and Megafunctions as plain text, except for some complex IP and some libraries that play a specific role in IP protection.  

 Hiding components that could be instructive otherwise effectively invalidates the example designs. If I understand right, there has been a discusion, that more Dev. Kits should be originated from Altera if possible. The said example design seems to emphasize these considerations.