NIOS PIO Interrupt

Altera_Forum · ‎10-04-2005

Hello all,

I am monica from germany.I am using NIOS in cyclone FPGA.I have problem

with PIO interrupts.

Environment details

Quartus Software : version 4.2 build 178 01/19/2005 SJ full version

Nios software : version 1.1.0 build 137

FPGA : Altera cyclone

I have a input signal which should generate interrupt on every rising

edge.So I have used a PIO to capture the signal and generate the IRQ

for every rising edge.

PIO settings :

width : 1bit

direction : input only

Edge capture reg

synchronously capture : yes

rising edge :yes

generate irq : yes

edge : yes

The software hangs at

"alt_irq_register(TEST_CONTINUE_PIO_IRQ,(void

*)&global_flag,&intr_timer);"

However software works fine,If I change the PIO settings to

width : 1bit

direction : input only

Edge capture reg

synchronously capture : yes

rising edge :yes

generate irq : yes

level : yes

I am trying to find out what might be causing my software hang if I use

"edge" instead of "level".

Did anybody face this sort of wierd behaviour? or is this a bug in

Quartus software?

I am wasting lot of time trying to solve this problem,I hope it is not a bug which I cant solve.

I will be obliged if anybody can give me some hint how to proceed further.

Thanking you,

Monica Dsouza

Altera_Forum · ‎10-04-2005

With the level interrupt turned on as long as the hardware line is asserted the interrupt will be asserted. To get out of continuous interrupt processing you would need to disable the interrupt inside the interrupt handler or cause the input to the PIO to no longer be asserted.

This isn't the case with the edge sensitive interrupt because the interrupt cause is transient (only when the input changed state).

Altera_Forum · ‎10-05-2005

I think you have to write something to the edge-detect register to get it to clear the edge-detect flags. If you don't, the interrupt condition will always be present and you'll keep re-entering the ISR.