SPI PUZZLE

[Altera_Forum]

Hello, all 

I have problems with SPI as follows. As you know, SPI is a 3 wire interface and  a SPI should have 3 signals commonly,  but in SOPC Builder, a SPI have 4 signals actully. They are sclk, ss_n, mosi and miso. Why? Generally speaking, a chip(such as TLV320AIC23B, which is a stereo audio codec) with SPI interface has 3 SPI pins, and they're clk, ss and data, which  is a bidirector signal.Suppose that the SPI is configured  as master, and an off-chip device with SPI interface is  configured as slave. Then, how should I connect them?  And what functions the signal of miso acts in this instance? Anyone can help me? Thanks.

[Altera_Forum]

eltonlaonong, 

 MOSI means Master-Out-Slave-In and is the data line transfering data from a Clock-Master to a Clock-Slave. And so is MISO the other data line from Slave (Out) to Master (In). This is a full duplex connection with multiple slaves (each selected and activated by a own SS ) and one Master, who provides clock and all slave select signals (SS). Most of the SPIs use this organization.  Mike

[Altera_Forum]

Hi, 

 > Then, how should I connect them?    Because SPI core data in/out port are mono-direction, but slave-device data port is bi-direction. So, you should add a tri-buffer to connect between device and master. ss_n is the output-en for tri-buffer.  LiangYi

[Altera_Forum]

Hi, 

 > Then, how should I connect them?   Because SPI core data in/out port are mono-direction, but slave-device data port is bi-direction. So, you should add a tri-buffer to connect between device and master. ss_n is the output-en for tri-buffer.  LiangYi

[Altera_Forum]

TLV320AIC23B datasheet: 

 Interface can work in SPI or I2C (twowire) mode  in SPI Mode:  SPI Signals are : \CS,SCLK and SDIN   SDIN is input only in SPI Mode  (it seems that register of AIC23 are write only)   so connect MOSI with SDIN

[Altera_Forum]

--- Quote Start ---  originally posted by fischer@Oct 10 2005, 05:59 AM tlv320aic23b datasheet:  interface can work in spi or i2c (twowire) mode  in spi mode:  spi signals are : \cs,sclk and sdin   sdin is input only in spi mode  (it seems that register of aic23 are write only)   so connect mosi with sdin <div align='right'><{post_snapback}> (index.php?act=findpost&pid=10261)  --- quote end ---    --- Quote End ---     So, in Quartus II, how to deal with the signal of miso generated by SPI core in SOPC Builder?  Thank you!

[Altera_Forum]

You can also look up at <n2cpu_nii5v3.pdf> Fig 7-4. 

Something like as LiangYi said.

[Altera_Forum]

Refe to <n2cpu_nii5v3.pdf> Fig 7-4 . 

something like as LiangYi said

[Altera_Forum]

--- Quote Start ---  originally posted by eltonlaonong@Oct 10 2005, 07:08 PM so, in quartus ii, how to deal with the signal of miso generated by spi core in sopc builder?  --- Quote End ---   Tie it off to VCC or GND if you&#39;re not using it. The synthesizer will optimize out the unused registers that way.

[Altera_Forum]

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif  

Thank u very much! I have made it clear with your help. Best regards!