ADC code for Cyclone II DE1 board not working

[Altera_Forum]

Hi, i wrote the following code to read digital values from the pins of ADC0804 but it doesnt seem to be working... 

 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library std; use std.standard;   ENTITY ADC IS  PORT( CLK : IN STD_LOGIC;  IN_0 : IN STD_LOGIC;--LSB  IN_1 : IN STD_LOGIC;  IN_2 : IN STD_LOGIC;  IN_3 : IN STD_LOGIC;  IN_4 : IN STD_LOGIC;  IN_5 : IN STD_LOGIC;  IN_6 : IN STD_LOGIC;  IN_7 : IN STD_LOGIC;--MSB  ADC_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ADC; ---------------------------------------------------------------- ARCHITECTURE a OF ADC IS  SIGNAL ADC_IN : STD_LOGIC_VECTOR(7 DOWNTO 0);     BEGIN    ADC_IN <= IN_7&IN_6&IN_5&IN_4&IN_3&IN_2&IN_1&IN_0;    PROCESS(CLK)  BEGIN    IF (CLK'EVENT AND CLK='1') THEN      ADC_OUT <= NOT(ADC_IN);   END IF;  END Process;      end a;      I tested this code using an 8 bit random number generator and it works fine, but when the cyclone II board is connected directly to the ADC0804, i get no output. The ADC is working fine(tested using array of LEDs)....  What am i doing wrong? please help me guys, this is urgent :(  or is it because of logic voltage levels? ADC0804 = 5V and 0V... Cyclone II FPGA = 3.3V and 0V...   ADC0804 is TTL compatible    Regards Dante

[Altera_Forum]

Hi, 

 what about the control signals like CS,RD,WR and INTR? are you applying the correct logic for these signals?   Regards,   Shahzad

[Altera_Forum]

--- Quote Start ---  Hi,   what about the control signals like CS,RD,WR and INTR? are you applying the correct logic for these signals?   Regards,   Shahzad  --- Quote End ---    Hi Shahzad, thanx for quick response... CS & RD are grounded, WR & INTR are connected together for continuous conversion and testing the circuit with LEDs it works... So i dont know what the problem is.. :(

[Altera_Forum]

Hi, 

 i dont think there is any promblem with the code. you should check if the FPGA pin assignment is done correctly... Since the chip is TTL competilbe, it must not have any promblem with 3.3 volt. Also you must power the ADC chip through power of DE1 board so that both the FPGA and ADC chip have same ground.   Regards,   Shahzad

[Altera_Forum]

Thanx Sha, thats exactly what i did, but i'll just go through it again and check if the pins are correctly assigned and if i still experience any problem, i will let you know. Thanx bro 

 Regards

[Altera_Forum]

--- Quote Start ---  Thanx Sha, thats exactly what i did, but i'll just go through it again and check if the pins are correctly assigned and if i still experience any problem, i will let you know. Thanx bro  Regards  --- Quote End ---     Hi,  how does the design inside the FPGA lookslike ? Is it only a feedthrough of the ADC data ? If not maybe you have a problem inside of your design. To check of your ADC data goes inside the FPGA corretly could be observed with signaltap.   Kind regards  GPK

[Altera_Forum]

--- Quote Start ---  Hi,  how does the design inside the FPGA lookslike ? Is it only a feedthrough of the ADC data ? If not maybe you have a problem inside of your design. To check of your ADC data goes inside the FPGA corretly could be observed with signaltap.   Kind regards  GPK  --- Quote End ---    Hi Pletz, Thanx for reply  I see this signaltap thingy, but hw does it work? hw do i see the signals?  Regards

[Altera_Forum]

The DE1 board is still not inputing anything :(, tried using the signaltap module but i just get license errors n then my design doesnt wanna compile anymore because of this error, luckily i had back up. i really dont know what to do anymore :( :( :(

[Altera_Forum]

Got it finally, Thanx Guys:D!!!

[Altera_Forum]

--- Quote Start ---  Got it finally, Thanx Guys:D!!!  --- Quote End ---    Hi,  in case you are using the web edition of Quartus you have to switch on the "TalkBack" feature. This should solve the licence problem. Otherwise you have to disable your signaltap file. You find the setting under: Assignments -> Settings -> Signaltap II Logic Analyzer   Kind regards  GPK

[Altera_Forum]

dante: can u help me?how do you do?plzz help me

[Altera_Forum]

--- Quote Start ---  dante: can u help me?how do you do?plzz help me  --- Quote End ---   help you with what?

[Altera_Forum]

I see ur adc run rite.. Are u have complete ur Project?? Can u give ur email we discuss it at email

[Altera_Forum]

--- Quote Start ---  I see ur adc run rite.. Are u have complete ur Project?? Can u give ur email we discuss it at email  --- Quote End ---    yes, i completed the project. so i see you want to use ADC0804. there's application note in the ADC0804 datasheet, did you have a look at it?

[Altera_Forum]

Yup i want use it.. Where part in datasheet?? Can u help me. I first time in fpga.. Can u give me cct of adc ??

[Altera_Forum]

which FPGA are you using for your project?