derive_pll_clocks -- partial clock creation

[Altera_Forum]

Is derive_pll_clocks similar to derive_clocks in the sense that it does not create a generated clock on pll outputs that are not connected in the design. From what I can tell, this is the case, but I want to be sure that this is the expected behavior.:confused:

[Altera_Forum]

Yes, that is correct.

[Altera_Forum]

--- Quote Start ---  Is derive_pll_clocks similar to derive_clocks in the sense that it does not create a generated clock on pll outputs that are not connected in the design.  --- Quote End ---     I think that derive_pll_clocks and derive_clocks are similar as far as the quoted statement goes (I didn't actually test them with unconnected PLL outputs), but these two commands have very different purposes.  derive_pll_clocks constrains all PLL output clocks and optionally PLL input clocks to match the PLL megafunction settings. The use of derive_pll_clocks is highly encouraged, although TimeQuest will give you a warning if manually created clock constraints do not match the megafunction settings.  derive_clocks creates an identical base-clock constraint on all not-already-constrained clocks in the design even if in reality some of the clocks should be constrained with generated clocks. The use of derive_clocks is discouraged. Even if all clocks in your design happen to run at the same frequency, it is better to constrain each clock individually with manual create_clock and create_generated_clock constraints or with derive_pll_clocks.   On-line help for the commands:     --- Quote Start ---  derive_pll_clocks  --------------------------------------------------------------------------------  The following table displays information for the derive_pll_clocks Tcl command:  syntax  derive_pll_clocks [-h | -help] [-long_help] [-create_base_clocks] [-use_tan_name]   arguments  -h | -help  Short help   -long_help  Long help with examples and possible return values   -create_base_clocks  Creates base clocks on input clock ports of the design that are feeding the PLL   -use_tan_name  Use net names as clock names     tcl package and version  Belongs to ::quartus::sdc_ext 1.0   description  Identifies PLLs or similar resources in the design and creates generated clocks for their output clock pins. Multiple generated clocks may be created for each output clock pin if the PLL is using clock switchover, one for the inclk[0] input clock pin and one for the inclk[1] input clock pin.  By default this command does not create base clocks on input clock ports that are driving the PLL. When you use the create_base_clocks option, derive_pll_clocks also creates the base clock on an input clock port deriving the PLL. This option does not overwrite an existing clock.  By default the clock name is the same as the output clock pin name. To use the net name (the same name the classic Timing Analyzer would use), use the -use_tan_name option.   example usage  project_open top create_timing_netlist  # Create the base clock for the input clock port driving the PLL create_clock -period 10.0 [get_ports sysclk]  # Create the generated clocks for the PLL. derive_pll_clocks  update_timing_netlist  # Other user actions report_timing  delete_timing_netlist project_close  --- Quote End ---       --- Quote Start ---  derive_clocks  --------------------------------------------------------------------------------  The following table displays information for the derive_clocks Tcl command:  syntax  derive_clocks [-h | -help] [-long_help] -period <period_value> [-waveform <edge_list>]   arguments  -h | -help  Short help   -long_help  Long help with examples and possible return values   -period <period_value>  Speed of the default clock in terms of clock period   -waveform <edge_list>  List of edge values     tcl package and version  Belongs to ::quartus::sdc 1.5  description  Creates a clock on sources of clock pins in the design that do not already have at least one clock sourcing the clock pin. This command is equivalent to calling create_clock on each clock source in the design that does not already have a clock assigned to it.  See the help for create_clock for more information.  altera does not recommend using this command during final sign-off analysis of a design. derive_clocks should only be used early in the design phase when the clocks are not completely known. When possible, create_clock and create_generated_clock should be used instead.   example usage  # Automatically create a 10ns, 60% duty cycle clock on all # unconstrained clock sources derive_clocks -period 10 -waveform {0 6}  --- Quote End ---  

[Altera_Forum]

I need a good information about how work with constrains !! 

 Any documentation (or pointers to documentation ) , examples would be appreciated.   Tx

[Altera_Forum]

At www.altera.com, do a site search for "TimeQuest resource center". The TimeQuest Timing Analyzer Resource Center should be the first search hit. That page lists links to design examples, training, and other documentation.