Cyclone III + EPCS + Remote Update

[Altera_Forum]

As the title suggests, we want to implement the remote update feature using the CIII and (Active Serial) EPCS64 device. The objective is to get two application programs stored on the EPCS device, both fpga bit configuration as well as the nios software. 

 I've searched this site for info on a complete start-to-finish solution that someone has already had success with. Altera has app note AN521 (http://www.altera.com/literature/an/an521.pdf), but it is specifically for the Active Parallel design.   Does Altera have a similar document for Active Serial devices? Or have they discovered that it is impossible to this with EPCS devices and aren't spreading the word?

[Altera_Forum]

I have successfully implemented a system which uses remote update with active serial configuration. 

 Altera's documentation definitely seems lacking in this area. I got it working based on AN429 and the Cyclone III handbook. A scope on the SPI lines to the memory and other configuration related signals was also a big help.  In the end, I created my own SPI component and software for writing and reading to the flash memory. The tricky part was then figuring out how to control the remote update hardware to trigger the reconfig to the application image.

[Altera_Forum]

"""The tricky part was then figuring out how to control the remote update hardware to trigger the reconfig to the application image.""" 

 Hi kevin how did you achieve reconfiguration successfully...cause am right now stuck in this thing...   please tell whether you converted the application elf file to flash and then to binary ....and then did you flash this binary to the location and triggered reconfiguration...   and also please let me know the steps for reconfiguration....   any help would be highly appreciated... thanks a lot in advance

[Altera_Forum]

It's been a while, so I don't remember all the details.  

 I added a "Remote Update Controller" in SOPC builder. To trigger the reconfig, you then do something like this:  // set address IOWR(CYCLONEIII_BASE, 0x04, nAddress >> 2); // disable watchdog timer IOWR(CYCLONEIII_BASE, 0x03, 0); // reconfig IOWR(CYCLONEIII_BASE, 0x20, 1);In my case, I was only using internal block RAM for my NIOS code. Therefore, I did not have a seperate ELF file to worry about as all my code was included in the SOF file. I used the sof2flash utility to generate a S record file which contained the data to flash to the EPCS.

[Altera_Forum]

Any clues if altera will update AN379 ? 

It still does not use some of the new features of the ASMI megafunction, and would be a good basis to start a RSU system without NIOS.

[Altera_Forum]

I got a confirmation from Altera that AN379 is outdated and one should use ATLASMI_PARALLEL instead

[Altera_Forum]

Try this: http://www.grigaitis.eu/?p=514 it worked to me.

[Altera_Forum]

Hello - I have a question about using the RSU core as well. Same situation, I am using a Cyclone III & EPCS w/ Remote Update except that I am not using a NIOS core, just user logic to both update the FLASH (via PCI) and to configure the RSU macro and enable re-config. 

 So, everything is in place and appears to be functioning OK, I have an image that includes signal tap and can see many of the internal signals.   When I do a write to param "100", I get a BUSY indication back from the core. When BUSY goes away, I do a read of param "100" and again see the BUSY signal asserted but the data returned is always "00000000".    I have the RD_SRC set to "00" for both the write and read - according to the liturature, this is supposed to be the current state contents in the status register.   If I keep walking through addresses, I can see the data I wrote to param "100" with RD_SRC = "00" show up at param = "100" but the RD_SRC = "11".   Any thoughts on this behavior? I am running w/ a user clock of 33Mhz and can see no limitatons for it's speed. Does anyone know if there is a maximum clock freq that can be used with this core?   Thanks Kevin.

[Altera_Forum]

Though I don't recall, exactly, I "think" that altremote_update has a limit of 25MHz...at least on CIII, that is. Go take a look at the Application Selector design for the NEEK and you'll see what the requirements are....with a Nios II, of course. 

 You know, you could go with the Nios II/e. It's now completely free, includes source code, and takes up hardly any resources.  Cheers,  -slacker

[Altera_Forum]

Slacker - thanks for your response, I did try this with an 11Mhz clock but see the same behavior.  

 I am running with the image loaded from sector 0x0 so I believe I am in Factory Config mode and since the data I write does come back on a read... albiet from the wrong address, it seems to be accepting the write. I just don't understand why I can't read from the offset that I am writing.     Thanks Kevin.

[Altera_Forum]

Hi Kevin, 

 What are you using to read/write to the EPCS (SPI flash)? I've only ever used the epcs_controller in an SOPC Builder system with Nios II. Doing it this way, I read/write to the EPCS using the epcs_controller and use the altremote_update block to trigger appropriate resets...  Regards,  --slacker

[Altera_Forum]

I am using the ASMI block. I ported the Altera code and added a state machine to interface to my code.  

 So, I realized I did not have the latest user guide for the Megafunction. I downloaded that and see that Altera now lists the max clock freq for each device. For a Cyclone III it is 40Mhz.   The new UG also includes an update to the READ_SOURCE table which shows a value of "11" as being the input register. That makes sense looking at the block diagram provided in the Cyclone datasheet since READ_SOURCE appears to be a mux select for the readback path.   Also included is an updated table of operations which is helpful too.    RTFM right?   Next up is to move a new image into FLASH and hit the reconfig pin.   Thanks Kevin.

[Altera_Forum]

Hi  

 I am using EPCS controller built using SOPC builder(Q9.0), FPGA device is Cyclone III and configuration device is EPCS16. I am using external processor to communicate with EPCS16 via Avalon Master, SOPC Fabric and EPCS controller (NIOS is NOT used).  I have user logic state machines written for factory and application image configurations. I have simulated/verified Data transfer from my remote update logic to ASMI megafunction & EPCSmemory model u.  I have one question: I have included Remote update controller & EPCS in the SOPC builder while generating the system. Do I have to include ASMI in the SOPC builder while generating the system?  Greatly appreciate your time!  Thanks, Brunda

[Altera_Forum]

In SOPC builder,now,I have Remote System Upgrade(RSU) and EPCS. 

Both connected to NIOS. But,how do I connect RSU and EPCS in SOPC builder?  When I use the RSU megafunction-cycloneIII ,it doesn't have ASMI ports to connect to ASMI. So,how does rsu communicate with epcs (to load factory configuration from epcs)?  I am using EPCS controller built using SOPC builder (Q10.0), FPGA device is Cyclone III and configuration device is EPCS16.  I have user logic state machines written for factory and application image configurations.And,an image update logic to load new image through ASMI.

[Altera_Forum]

Brunda: 

Double posting is not good, it's confusing to someone seeking an answer and having to read the same question multiple places, but the answer in a single place. PLEASE do not double post.  Your answer is here: http://www.alteraforum.com/forum/showthread.php?t=18610&page=7  Basicaly: you do not need to connect the RSU and you do not need to connect the EPCS. But you do need to write software for them.

[Altera_Forum]

Thanks for your reply.I didnt realize that I have posted my question twice. 

Sorry for the inconvenience. Can you please point me any document which describes the software needs to be written for these blocks to work. Thanks again.

[Altera_Forum]

The link to the grigaitis website has been useful for me, but I only managed to get the remote update working after I added a delay as follows:- 

 IOWR(remote_update_base, 0x4, reconfig_offset >> offset_shift); // *** delay added *** delay_us(100); // Perform the reconfiguration by setting bit 0 in the // control/status register IOWR(remote_update_base, 0x20, 0x1); The delay routine is my own crude for() loop, so I'm not sure how long I *really* needed to wait ... but it works for me !! :)  It may be due to me using a full NIOS core running @ 40MHz ... who knows !?!

[Altera_Forum]

I am using EPCS controller built using SOPC builder(Q9.0), FPGA device is Cyclone III and configuration device is EPCS16.  

 I have user logic state machines written for factory and application image configurations. I have simulated/verified Data transfer from my remote update logic to ASMI megafunction & EPCSmemory model.  I am using EPCS,ASMI 7 remote sys upgrade mega functions.I didnt use them in SOPC builder.  Now,I am trying to program FPGA using jic file which is converted from sof file.It wont let me program without SFL(Serial Flash Loader.)  How I can avoid using the SFL in my application?  Looking forward for your help!

[Altera_Forum]

--- Quote Start ---  It's been a while, so I don't remember all the details.   I added a "Remote Update Controller" in SOPC builder. To trigger the reconfig, you then do something like this:  // set address IOWR(CYCLONEIII_BASE, 0x04, nAddress >> 2); // disable watchdog timer IOWR(CYCLONEIII_BASE, 0x03, 0); // reconfig IOWR(CYCLONEIII_BASE, 0x20, 1);In my case, I was only using internal block RAM for my NIOS code. Therefore, I did not have a seperate ELF file to worry about as all my code was included in the SOF file. I used the sof2flash utility to generate a S record file which contained the data to flash to the EPCS.  --- Quote End ---    Hi, kevin   Would you tell where theses code locate? In factory nios program or application nios program? I'm now very confusing with this issue. I want to figure out the reconfiguration process.  Thank you in advance! -wei

[Altera_Forum]

Hi fifamanutd, this code is an example code to configure and trigger the reconfiguration. You can use the remote_update core on both images (same for the code) if you want to switch between imagens whenever you feel like, but you need to have it at least at factory image... 

 Try reading the Remote Update Megafunction User Guide and the SOPC Remote Update user guide (Embedded Peripherals IP User Guide).  Cheers

[Altera_Forum]

Hi wgutstein, 

Thank you for your reply. I just figured all my questions out and realized a remote update system in my board yet.  Thank you all.