what is wrong in this VHDL code?

[Altera_Forum]

Hey guys  

i have this VHDL code but when i compile it i got an error message thx said: Error (10818): Netlist error at DSS_LUT.vhd(21): can't infer register for Hex_out[8] because it does not hold its value outside the clock edge. This is the code : library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;  entity DDS_LUT is port (  clk : in std_logic;  --encoder_a : in std_logic;  data_b : in integer range 3185 to 4215 ; --std_logic_vector(12 downto 0);  Hex_out : out std_logic_vector (30 downto 0) --(need output with hexa not bin)   ); end; architecture arc_DDS_LUT of DDS_LUT is begin   process (data_b)  begin   if CLK'EVENT and CLK = '1' then  case data_b is  when 3185=> Hex_out <= ("1010101101110111011101110111100");   when 3186=> Hex_out <= ("1010101101101001110100000011011");  when 3187=> Hex_out <= ("1010101101011100001010001111011");  when 3188=> Hex_out <= ("1010101101001110100000011011010");  when 3189=> Hex_out <= ("1010101101000000110110100111010");  when 3190=> Hex_out <= ("1010101100110011001100110011001");  when 3191=> Hex_out <= ("1010101100100101100010111111001");  when 3192=> Hex_out <= ("1010101100010111111001001011001");  when 3193=> Hex_out <= ("1010101100001010001111010111000");  when 3194=> Hex_out <= ("1010101011111100100101100011000");  when 3195=> Hex_out <= ("1010101011101110111011101110111");  when 3196=> Hex_out <= ("1010101011100001010001111010111");  when 3197=> Hex_out <= ("1010101011010011101000000110110");  when 3198=> Hex_out <= ("1010101011000101111110010010110");  when 3199=> Hex_out <= ("1010101010111000010100011110110");  when 3200=> Hex_out <= ("1010101010101010101010101010101");  when 3201=> Hex_out <= ("1010101010011101000000110110101");  when 3202=> Hex_out <= ("1010101010001111010111000010100");  when 3203=> Hex_out <= ("1010101010000001101101001110100");  when 3204=> Hex_out <= ("1010101001110100000011011010011");   when 3205=> Hex_out <= ("1010101001100110011001100110011");  when 3206=> Hex_out <= ("1010101001011000101111110010011");  when 3207=> Hex_out <= ("1010101001001011000101111110010");  when 3208=> Hex_out <= ("1010101000111101011100001010010");  when 3209=> Hex_out <= ("1010101000101111110010010110001");  when 3210=> Hex_out <= ("1010101000100010001000100010001");  when 3211=> Hex_out <= ("1010101000010100011110101110000");  when 3212=> Hex_out <= ("1010101000000110110100111010000");  when 3213=> Hex_out <= ("1010100111111001001011000110000");  when 3214=> Hex_out <= ("1010100111101011100001010001111");  when 3215=> Hex_out <= ("1010100111011101110111011101111");  when others => Hex_out <= ("1111111111111111111111111111111");  end case;  else   Hex_out <=("0000000000000000000000000000000");  end if;   end process; end arc_DDS_LUT ;   what the code should do is : every time there is a rising edge I will check the input number I got and give an output number from the case statement

[Altera_Forum]

You need to add your clock to the sensitivity list. It should be "process (CLK, data_b)" instead of "process (data_b)". 

 You should also remove the "else" clause after your case since it will clear your outputs anytime there is a change in the signals specified in the sensitivity list that doesn't correspond to a rising edge of clk. In other words if the input data_b changes then your process is evaluated and the outputs will be cleared.  For style look into two alternative coding details: (a) You can use the "rising_edge" function which is part of the IEEE std logic library. (b) You can use Hex notation instead of the binary strings.

[Altera_Forum]

Do you want only combinational logic or do you want hex_out to be flip-flops? You've combined the constructs for just combinational logic and logic with flops. 

 If you want just combinational only, drop the CLK references, and drop the "else hex_out <=("0000000000...000");" fragment  If you want logic followed by flops, change the sensitivity list for the process to be CLK, not data_b, AND drop the else hex_out <=("0000000000...000");" fragment.  \c

[Altera_Forum]

For sure I'm no expert in VHDL and maybe there are more elegant solutions, but the following should work: 

----------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;  entity DDS_LUT is port ( clk : in std_logic; --encoder_a : in std_logic; data_b : in integer range 3185 to 4215 ; --std_logic_vector(12 downto 0); Hex_out : out std_logic_vector (30 downto 0) --(need output with hexa not bin)  ); end; architecture arc_DDS_LUT of DDS_LUT is  signal hex_out_internal : std_logic_vector (30 downto 0); begin   hex_out <= hex_out_internal;  -- or maybe: Hex_out (30 downto 0) <= Hex_out_internal (30 downto 0);  process (clk) begin  if CLK'EVENT and CLK = '1' then case data_b is when 3185=> hex_out_internal <= ("1010101101110111011101110111100");  when 3186=> hex_out_internal <= ("1010101101101001110100000011011"); when 3187=> hex_out_internal <= ("1010101101011100001010001111011"); when 3188=> hex_out_internal <= ("1010101101001110100000011011010"); when 3189=> hex_out_internal <= ("1010101101000000110110100111010");  .... and so on  -----------------------------------------  Hope this helped :)  Right: sensitivity list should be changed, too.

[Altera_Forum]

You've already gotten some good responses. In case it wasn't already apparent, you are getting that error because of the statement: 

else Hex_out <=("0000000000000000000000000000000"); This makes your code unsynthesizable. What you are telling Quartus II to do is "when there is a clock transition do this, when there is not a clock transition do that." The problem being, a clock transition is "true" for an infinitesimally short amount of time. So, what you want to tell Quartus II to do is "after a clock transition, do this." You can do that be removing the 'else' statement. You never want an 'else' or 'elsif' with your if (clk'event).

[Altera_Forum]

Thanks u all guys