how set minimu delay (constraint) with TIMEQUEST

[Altera_Forum]

Hello, 

 In attach file small project example.  I modified file “rx_clk.sdc” with timequest.   Because I want set a min or max delay path between two register  If you open rx_clk.sdc you can see this line    set_min_delay -from [get_pins {Fdata_un|regout}] -to [get_pins {Fdata_deux~reg0|datain}] 5.000  set_min_delay -from [get_registers {Fdata_un}] -to [get_registers {Fdata_deux~reg0}] 10.000    However I recompile my quartus project with this constraint file and any delay path is modified.    Someone can help me to modify delay path in my project.  Just an example

[Altera_Forum]

1) I saw this was last compiled in Q6.1. I used Q8.0 and would recommend upgrading, as TimeQuest has steadily improved with each release. Nothing overly drastic, but a lot of usability enhancements. 

2) Assignments -> Settings -> Timing Analysis -> Use TimeQuest radio button. Right now you have selected the Classic Timing Analyzer, which means to completely ignore your .sdc file. 3) Assignments -> Settings -> Fitter -> Optimize Hold Timing -> All Paths. It's default value is to just add delays for I/O paths, i.e. it won't add delay to fix hold requirements internally. The reason this is the default is designers often make gated clocks that introduce all sorts of difficult hold requirements, where it's best for the designer to change the code(use a PLL, clock enable or altclkctrl, depending on what they're doing), rather than have Quartus fix it. Otherwise Quartus will tend to mask the problem. 4) Finally, I just wanted to point out that set_min_delay and set_max_delay assignments do take into account clock delays(skew). Many people don't realize this, and think it's a point to point assignment. The fact that it uses clock delays is a very good thing, since the relationship between two registers is dependent on clock delays as much as the data delay between them. You'll see this once you analyze the path in TQ.

[Altera_Forum]

I'm desperate for this problème 

I don’t understand why the path doesn’t change with this procedure follow:  In Timequest I measure the path with report path.  I set in sdc file    set_min_delay -from [get_pins {Fdata_un|regout}] -to [get_pins {Fdata_deux~reg0|datain}] 5.000  set_min_delay -from [get_registers {Fdata_un}] -to [get_registers {Fdata_deux~reg0}] 10.000    I write the new sdc file.  I compile project with the sdc file  Timequest is enable  Sdc file is added to project  Assignments -> Settings -> Fitter -> Optimize Hold Timing -> All Paths. Is set  After the compilation I reopen timequest and measure the delay path.  Any difference.  Why????    Thank for you help

[Altera_Forum]

You have conflicting assignments. Your clock requirement is 1ns(1GHz), which means the path between registers has to be less than 1ns. You then add a min requirement that says it has to be greater than 5ns and 10ns. Quartus II probably doesn't know what to do. I changed the clock to: 

create_clock -name Din -period 20.000 [get_ports {Din}]  (I removed the -waveform, as the default is a 50/50 duty cycle, and I've seen users forget to change it when they change the period, which naturally is incorrect...)  Now we have a default setup requirement of 20ns, a default hold requirement of 0ns, and on the two paths you overrode the default hold requirement with 5ns and 10ns. (Looking closer, you still have a problem in that you've constrained the same path twice, once at 5ns and once at 10ns. The second one takes affect...)  Anyway, making that clock constraint and looking at the hold timing on that path, a 10ns route has been added by Quartus to meet hold timing.   Why are you adding delays to internal paths? This is generally not recommended...

[Altera_Forum]

Thank for you help 

 If you look my attach design in cpd_top.vhd i recover a clock (rx clock) with input DIN and SIN. And for my design i need path delay rx clock greather than path DIN. therefore i want expand path of DIN.  i need respect the rule PATH DIN < PATH rx_clk - setup flip flop   thank you excuse for my bad english

[Altera_Forum]

attach file

[Altera_Forum]

Thank you help: big Guru thanks to you i set a mini constraint with time quest 

betwen two flip flop