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DDR2 cyclone III FPGA dev kit

Altera_Forum
Honored Contributor II
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Hello, 

 

I would like buy the Cyclone III FPGA dev kit. I see that they are on the kit 5 case of DDR2 SDRAM. So I would like know if the code for read and write on the cases is include in the kit. And if someone has ever use this kit and the DDR2 SDRAM. 

 

Thinks,
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Altera_Forum
Honored Contributor II
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Yes, the standard nios II example given with the development board includes the ddr2 controller megafunction, correctly configured and connected for the kit. It is only connected to 2 of the 5 chips though ("DDR2 bottom")

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Altera_Forum
Honored Contributor II
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Ok thinks, but when I want compile this exemple (nios 2 exemple) I have 4 errors.  

 

Had you the same problem then you had comile the project? 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=506  

 

But I have look the SOPC Builder of the exemple and I have see that only one case is use for the exemple.
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Altera_Forum
Honored Contributor II
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No I didn't have this problem. You should look at the messages before the "Can't fit design in device" to find where the problem comes from. 

Did you make any change to the example design before compiling it?
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Altera_Forum
Honored Contributor II
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No I have just open the project and compile the file! Nothing else. 

 

I use quartusII v8.0 

 

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Altera_Forum
Honored Contributor II
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I still use Quartus II 7.2 SP3. Could you copy/past or upload the processing information you have in quartus' log before the "can't fit" error message?

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Altera_Forum
Honored Contributor II
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I will go try to install quartus II 7.2 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=507
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Altera_Forum
Honored Contributor II
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It seems that Quartus has trouble processing the timing constraints file for the DDR controller. I'm not sure what's wrong exactly, but you should definitely try with 7.2 and see if you have the same problem. 

Do you have any messages between the "Reading SDC file: 'altmemddr_phy_timing.sdc'" line and the big error message on the top of your screenshot?
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Altera_Forum
Honored Contributor II
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No there is any message between the "Reading SDC file: 'altmemddr_phy_timing.sdc'" line and the big error message on the top of your screenshot. I will go install an old version of quartus and retry the operation 

 

Thinks
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Altera_Forum
Honored Contributor II
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are you sure you are picking the right device for the project?

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Altera_Forum
Honored Contributor II
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The device that I use is : 

 

EP3C120F780C8
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Altera_Forum
Honored Contributor II
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Do you know where I can download quartus II 7.2 

I went on the altera web site but I can download only the sp 2 ou 3 de quartus. But before install the sp 2 ou 3 you must install quartus II 7.2 

 

Thinks
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Altera_Forum
Honored Contributor II
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Don't you have the 7.2 CD in the box with the development board?

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Altera_Forum
Honored Contributor II
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The complete web version including SP3 is downloadable as well.

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Altera_Forum
Honored Contributor II
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I have not buy the kit, I want test the program in simulation before buy. 

I have download Altera II 7.2 sp3 but when I want install the soft, I have a problem. 

https://www.alteraforum.com/forum/attachment.php?attachmentid=511  

 

Because I have not quartus II 7.2  

 

So if someone know where I can download the sotf... 

 

Thinks
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Altera_Forum
Honored Contributor II
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Some one is arrive to compile the standard nios II example given with the development board cyclone III with quartus II 8.0 ? 

 

Thinks
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Altera_Forum
Honored Contributor II
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Altera_Forum
Honored Contributor II
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Thinks everyone, I have download quartus II 7.2 and I arrive at compile my project. But quartus put 20min for compile!!!!!! it is huge.

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Altera_Forum
Honored Contributor II
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double check on the device that u had selected in your project & verify that in ur pinmap..I mean QSF file

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