Serial/parallel interface

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[attachment=36:attachment][attachment=37:attachment]SERIAL/PARALLEL INTERFACE FOR USE WITH SOPC BUILDER AND NIOS II 

 parallel_to_serial_custom_peripheral_hw is a parallel-to-serial interface that can be used as a custom peripheral with SOPC Builder.  serial_to_parallel_custom_peripheral_hw is a serial-to-parallel interface that can be used as a custom peripheral with SOPC Builder.  These peripherals are intended to be used together to communicate between Altera FPGAs.  You may use these custom peripherals in your own design as-is or with your own modifications. These peripherals can be used as examples for generating your own custom peripheral with SOPC Builder and writing your own software for your peripheral.  Although these peripherals and the accompanying software are provided to you with no offer of technical support, your suggestions for improvement, identification of bugs, and comments on whether you found this useful would be appreciated. Send your feedback to bbuckman@altera.com.  The serial interface uses clock, enable, and data signals. The software can poll status registers or use interrupts to determine when the parallel-to-serial interface is ready to accept new data from the software for transmission and when the serial-to-parallel interface has received new data that is ready for the software to read.  The files as provided are configured to allow up to 32 bits of data. Software can set the data size to any number of bits from 1 to 32. To produce a smaller hardware implementation, define statements in the Verilog and C files can be modified to reduce the maximum number of allowed bits.  The Quartus project is set up for the EP1S10F780C6ES Nios development kit hardware. Modify the project as needed to work with other hardware.  See serial_parallel_custom_peripherals_readme.txt for more information.