Output Pins stuck at VCC or GND

[Altera_Forum]

Hi all. I've just finished writing and simulating a program which functions as a calculator.. However upon compiling the program, there is this warning which says: 

 "Output Pins stuck at VCC or GND".  Just so you all know I'm still relatively new to VHDL and am not particularly well versed yet. I wish to know how can I solve this problem. The pins are actually 2 pins which I intend to interface with a Seven Segment Display. And both pins are stuck at VCC, therefore permanently lighting those two LEDs.   I have two questions:  a) Why are those pins stuck at VCC when I did not assign any pins yet. b) How do I avoid this problem.  Thanks for those who can help.

[Altera_Forum]

I reviewed my previous explanation for synthesis failure of the design, and found, that's it not correct. Actually, LOADADR is active for one clock cycle, I didn't consider that STATE is a registered signal. So it's possibly a synthesis bug, as suspected. You should check, if the Stratix III design gives correct behaviour in Quartus timing simulation. 

 Sorry for causing confusion.  P.S.: Looking at a Quartus simulation, the receiver state apparently never reaches RECV_DATA, so all outputs are non-functional. Seems like Quartus synthesis came to the same result.

[Altera_Forum]

Hi FvM,too, 

'loadRDR' signal is not asynchronous logic,but has rising edge logic for the sentence bclkx8_rising='1'

[Altera_Forum]

Thanks,so frank of you! 

I will check the simulation output in another family.I will report to all of you tomorrow.Best regards

[Altera_Forum]

I find part of the answers! That was my fault while typing the codes.Here it was WHEN START_DETECTED=> 

IF BCLKX8_RISING='0' THEN  NEXTSTATE<=START_DETECTED;  ELSIF RXD<='1'..... The last sentence rxd should be rxd='1' !! I admire FvM who found that the state never reach RECV_DATA,How did you find that? It was very important clue.

[Altera_Forum]

I run the code in Quartus simulator (using Stratix III target). If it doesn't compile for this target, you need to use a functional simulator (e.g. ModelSim Altera Edition) or understand the problem from analyzing the code. 

 Personally, I try to have a more simple and "readable" FSM structure for similar purposes, using only one clocked process (a simplified "Moore" design). It helps to see this kind of problems, but can't avoid them completely.

[Altera_Forum]

That's the another clue! I'll remember it.Thanks again.Have a good weekeed,everybody

[Altera_Forum]

I'm having a bit of a problem with this myself. 

I'm trying to drive output pins with a constant driver in a couple of procedures. I also have a state machine where in it's first state, the output pins are all connected to ground. After it's first state (The init state) it shouldn't be tied to ground anymore!

[Altera_Forum]

and also, my design won't run in modelsim. 

And yes, I sis try making the DFT signal(meant to an input test for hardware testing) up in the entity, but it keeps complaining about the output driver.