Can't Read Data from Custom componet (Avalon mm)

[Altera_Forum]

I had associated a custom component (A variation of the DCFIFO example available in AN 473) to my NIOS 2 System. I use the Avalon MM (Slave) Interface whit the current signals: 

 Readdata (32bits) out Read (Used as the component read clock) IN  Everything goes right to me, till i try to read some data from the nios 2 software. (I use the HAL, avoiding any OS)   I can find the base address in System.h #define DCFIFO_DE_TOP_0_NAME "/dev/dcfifo_de_top_0"# define DCFIFO_DE_TOP_0_TYPE "dcfifo_de_top"# define DCFIFO_DE_TOP_0_BASE 0x00400000# define DCFIFO_DE_TOP_0_SPAN 4# define DCFIFO_DE_TOP_0_TERMINATED_PORTS ""# define ALT_MODULE_CLASS_dcfifo_de_top_0 dcfifo_de_top But, when i try to read some data from the component using the IORD macro  IORD(DCFIFO_DE_TOP_0_BASE,0);I only get zeros.  I know that i am missing something but i can't figured out what... }  Anything you can point will be useful.  jairo

[Altera_Forum]

read_i will only be active for one cycle (with the default timing parameters in the component builder) so why don't you just clear the irq signal and change to the correct state when read_i is 1?

[Altera_Forum]

In our design we have included a custom component into the SOPC design. The custom component (IMM, instance IMM_x) is connected to the write master port of a DMA. The DMA reads data from data_memory which is different from program_memory. Here is the definition of the custom component as seen in system.h 

   --- Quote Start ---  # define __IMM  /*  * IMM_x configuration  *  */ # define ALT_MODULE_CLASS_IMM_x IMM# define IMM_X_BASE 0x0# define IMM_X_IRQ -1# define IMM_X_IRQ_INTERRUPT_CONTROLLER_ID -1# define IMM_X_NAME "/dev/IMM_x"# define IMM_X_SPAN 536870912# define IMM_X_TYPE "IMM"   /*  * IMM_x configuration as viewed by DMA_x_write_master  *  */ # define DMA_X_WRITE_MASTER_IMM_X_BASE 0x0# define DMA_X_WRITE_MASTER_IMM_X_IRQ -1# define DMA_X_WRITE_MASTER_IMM_X_IRQ_INTERRUPT_CONTROLLER_ID -1# define DMA_X_WRITE_MASTER_IMM_X_NAME "/dev/IMM_x"# define DMA_X_WRITE_MASTER_IMM_X_SPAN 536870912# define DMA_X_WRITE_MASTER_IMM_X_TYPE "IMM"  --- Quote End ---    Can somebody tell me, how can I program it in C. I mean how should I configure the DMA to write to IMM_x. Thanks

[Altera_Forum]

Which DMA controller is it? Altera provides drivers with C functions that you can use to configure the DMA.

[Altera_Forum]

--- Quote Start ---  Which DMA controller is it? Altera provides drivers with C functions that you can use to configure the DMA.  --- Quote End ---    It's altera avalon DMA. Configuration of SOPC is shown in the figure. Can I access it like this, (where IMM_x, is the image of my custom made design)     --- Quote Start ---  alt_dma_txchan txchan; void* tx_data_to = IMM_X_BASE; //is it correct???????  alt_dma_txchan_ioctl(txchan, ALT_DMA_SET_MODE_32, NULL);  alt_dma_txchan_ioctl(txchan, ALT_DMA_TX_ONLY_ON, tx_data_to);  alt_dma_txchan_ioctl(txchan, ALT_DMA_RX_ONLY_OFF, NULL);   --- Quote End ---  

[Altera_Forum]

using IMM_X_BASE as an address is fine. But why don't you use the higher level HAL functions to configure the DMA? Functions like alt_dma_txchan_send() and alt_dma_rxchan_prepare() ? They are described in this document (http://www.altera.com/literature/hb/nios2/n2sw_nii52004.pdf), pages 6-25 and up.

[Altera_Forum]

alt_dma_txchan_ioctl is a higher level HAL function ;). 

With that code you will configure it to perform word transfers. And you will be constantly writing to the same address (tx_data_to) and the reading address increments by 0x04 after each read.   You can use the code on page 29 of the document Daixiwen linked. Just add the configuration like this: if ((txchan = alt_dma_txchan_open("/dev/dma_0")) == NULL) { printf ("Failed to open transmit channel\n"); exit (1); } else { alt_dma_txchan_ioctl(txchan, ALT_DMA_SET_MODE_32, NULL); alt_dma_txchan_ioctl(txchan, ALT_DMA_TX_ONLY_ON, tx_data_to); alt_dma_txchan_ioctl(txchan, ALT_DMA_RX_ONLY_OFF, NULL);  } 

[Altera_Forum]

--- Quote Start ---  I had associated a custom component (A variation of the DCFIFO example available in AN 473) to my NIOS 2 System. I use the Avalon MM (Slave) Interface whit the current signals:   Readdata (32bits) out Read (Used as the component read clock) IN   Everything goes right to me, till i try to read some data from the nios 2 software. (I use the HAL, avoiding any OS)    I can find the base address in System.h  #define DCFIFO_DE_TOP_0_NAME "/dev/dcfifo_de_top_0"# define DCFIFO_DE_TOP_0_TYPE "dcfifo_de_top"# define DCFIFO_DE_TOP_0_BASE 0x00400000# define DCFIFO_DE_TOP_0_SPAN 4# define DCFIFO_DE_TOP_0_TERMINATED_PORTS ""# define ALT_MODULE_CLASS_dcfifo_de_top_0 dcfifo_de_top But, when i try to read some data from the component using the IORD macro   IORD(DCFIFO_DE_TOP_0_BASE,0);I only get zeros.   I know that i am missing something but i can't figured out what... }   Anything you can point will be useful.   jairo  --- Quote End ---     Hi   I am also adding an avalon memory mapped slave, but not the FIFO one, to my nios 2 system. When I build my C code, everything is fine but cant run on hardware and I get this error message:   There are no Nios II CPUs with debug modules available which match the values specified. Please check that your PLD is correctly configured, downloading anew SOF file if necessary.   Please...Do you know what coud be the problem?