Maximum Number of DDR2 SDRAM Interfaces Supported per FPGA with Cyclone IV

Altera_Forum · ‎07-22-2010

Hello,

I am trying to use the Cyclone IV E with DDR2 SDRAM interfaces.

I have a question with the Maximum Number of DDR2 SDRAM Interfaces Supported per FPGA for Cyclone IV E in the documentation (Section III. System Performance Specifications) :

When it is said that on top side, for example, the Maximum Number of DDR2 SDRAM Interfaces is "one x 48 interfaces" or "two x 8 interfaces" it is not equivalent ! You can only reach an equivalent of "one x 16 interfaces" in the second case ?

I don't clearly understand what is a "x48" or "x8 interfaces". Is it the number of bits of Data bus ?

Does that mean that you can only use on this side either one DDR2 SDRAM interface with a 48-width of Data Bus, or two with an only 8-width of Data Bus ?

Thanks

Altera_Forum · ‎07-22-2010

You didn't mention which Cyclone IV E device you are using.

Table 7-2 of the user's guide is useful:

http://www.altera.com/literature/hb/cyclone-iv/cyiv-5v1-02.pdf

Yes the width refers to the number of bits on the data bus.

There are usually 3 constraints to consider for the limitation on number of memory controllers you can support:

1 - I/O pin limitations (this is the number of DQ groups available, and don't forget command / address pins).

2 - PLL limitations (you need a PLL per controller I believe).

3 - Internal resource utilization.

So on a EP4CE115 device in the 780 pin package; you could presumably have 6 x8/x9 groups on the top and/or bottom of the device. So to me this means you could have:

1 x48 DDR2 controller (6 groups of x8/x9)

2 x8/x9 DDR2 controllers (1 groups of x8/x9 each)

2 x16/x18 DDR2 controllers (2 groups of x8/x9 each)

2 x24/x27 DDR2 controllers (3 groups of x8/x9 each)

Now could you do 3 x8/9 interfaces. My gut tells me know. I'm thinking the PLL clocking is going to get hairy.

Jake

Altera_Forum · ‎07-23-2010

Ok thank you very much.

And do you know which size of DDR2 controller (1G, 2G, 4G...) is available with the Cyclone IV EP4CE115 in the 780 pin package ? What is the depth of DDR2 controller available with this device ?