SDRAM Controller

[Altera_Forum]

Now, i am researching about SDRAM Controller Core.So o need some document its.Can you help me? 

 Many thanks

[Altera_Forum]

Single data rate DRAM controller is available as an Altera reference design, much more complex double data rate DRAM controller as encrypted Altera IP core with user manuals, example projects, application notes and such.

[Altera_Forum]

have you got any document which is relative with sdr sdram controller?Can you post here?Thanks advance!

[Altera_Forum]

There has been an Altera White Paper sdr sdram controller from 2002 related to ref-sdr-sdram-vhdl.zip. I couldn't locate the document and the design now.

[Altera_Forum]

Huhu, i need it now.I'm doing final project in university.Help me, please

[Altera_Forum]

Either I missed the files at Altera site or they have been removed because of their age. However, I've been using a SDR controller based on this design recently.

[Altera_Forum]

I tried to find it on Altera's site, but I think it has been removed...I have a copy of the IP Core Manual that I renamed to sdr_sdram_tuning.pdf...It is the same manual though. I only renamed it to remind myself of the custom board pll tuning formulae that is in the appendix for phase delay shifting. Hope it can help 

 --Dan

[Altera_Forum]

Thanks u very much. can you explain to me the timing diagram of each module?EX: INIT_FSM module and CMD_FSM module?The relationship of each module with Signal Generation module? 

 Why can we use Phase lock loop?

[Altera_Forum]

Hichic, i dont know the pinouts, timing diagram and state machine of each module: INIT_FSM, CMD_FSM, COUNTER, SIGNAL GENERATION and DATA PATH. 

 Can you help me to solve?

[Altera_Forum]

I was aware now, that the other SDR DRAM IP core, Daniel was referring to, is the SDRAM Controller Megafunction available with SOPC Builder. The posted document is also part of Quartus II Version 7.2 Handbook, Volume 5 Embedded Peripherals. In contrast to the old SDRAM reference design, it has an Avalon interface with a FIFO, but it's also rather simple and could be used in a standalone application.

[Altera_Forum]

Nobody can help me to find pinouts, timing diagram, and state machine of each modules?Help me, please!

[Altera_Forum]

Hello, 

 I don't understand what you mean with pinout in this respect. The operation of the old Altera SDRAM controller reference design is described rather detailed in the included white paper sdr_sdram.pdf. It can be easily operated for moderate speed requirements, e. g. 100 MHz at Cyclone or Cyclone II. As additonal remark, it may be necessary to define fast IO register for datapath and control signals explicitely in pin planner or assignment editor.  Regards, Frank

[Altera_Forum]

Okay, thanks for your attach file.Have you got source code which uses verilog, not vhdl?Thanks again.

[Altera_Forum]

Hello, 

 here you have the Altera SDRAM controller used with SOPC builder, it's parametrized for a 128 MBit chip with 32 Bit data width. As already mentioned, it has an additional FIFO to match the Avalon interface used with Nios II.  Respective documentation had been posted by Daniel previously.  Regards, Frank

[Altera_Forum]

CH... 

 If you need something more graphical in nature to help you to understand the state machine switches you could go ahead and compile the design without connecting your top level SOPC Builder project i/o pins, and then use the Quartus graphical state machine viewer to study the behavior.   I am not sure what you hope to gain other than knowledge for knowledge sake. I don't know your level of knowledge, so forgive me if I insult you; but generally speaking, the state machines handle init cycles, precharge, and refresh commands, as well as placing the needed cs_n, ras_n, cas_n, & wr_n on the bus. This information is used in connection with the row, bank and column addresses to locate the storage position in sdram. There are many documents on this suject including the datsheet of the chip you are using that will provide you with their specific timimg requirements for parameterization of your controller module. Also, if you plan to use the pll to generate your external clock, I would suggest you start with a phase delay of -4ns for a custom board and work from there...agian all in the manual.  By the way, what is you preferred design flow? Are you aware that you can create a schematic, and use generated symbols to make your design visually? I have found that method beneficial at times over the homogenous verilog/VHDL approach.  --Daniel

[Altera_Forum]

Have you got the software which is translate VHDL to Verilog?

[Altera_Forum]

Hello, 

 Sorry to hijack this thread, but this seems like a good thread too.  I'm building a frame grabber using FPGA  I have decided to use c3088 camera which uses ov6620 from Omnivision on my project. I would like to grab 2 frames into the FPGA.  The camera has VSYNC, HREF, PCLK AND 8 bit for each pixel data. VSYNC tells us the start of a new frame, HREF tells us the start of new line while PCLK tells us a new pixel coming in.  The camera provides 352x292 pixel but I'm only interested in the 1st 50x50 of the frame in the upper left corner.  I would like to save the array of data into the SDR SDRAM.  I've read some other project which is somewhat similar to mine.  The fella build a component to receive the data from the camera in vhd and then add that component into sopc builder.  I've also build component that would able to extract the first 50x50 pixels. and this is where i couldn't go further.  The problem that im facing is how do i actually save this array of data into the SDRAM?  I didnt saw any megacore ip for this SDRAM but i do found that there's a sdram controller in sopc builder.  As, I'm quite new to this. I would like to know what is avalon in sopc builder, and what actually sopc builder do?  I followed the instructions for building a nios system. but how does this system actually helps me in saving the array of data in SDRAM?   What i know is that we can run C program in a nios ii system. but i do not need to run a c program for this system.

[Altera_Forum]

When i compile my code, i meets some error like that, can you help me? 

. . . reg regSysDX; . . . regSysDX <=# tDLY 16'h0000;  Warning: truncated value with size 16 to match size of targer . . .   reg syncResetClkCNT; . . .  syncResetClkCNT <=# tDLY (`endOf_Write_Burst) ? 1 : 0; Warning: truncated value with size 16 to match size of targer  syncResetClkCNT <=# tDLY (clkCNT == NUM_CLK_READ) ? 1 : 0; Warning: truncated value with size 16 to match size of targer  etc...

[Altera_Forum]

--- Quote Start ---  syncResetClkCNT <=# tDLY (clkCNT == NUM_CLK_READ) ? 1 : 0;Warning: truncated value with size 16 to match size of targer  --- Quote End ---   I would expect a warning value with size 32 in this case, cause integer values have 32 rather than 16 as default size.  If you examine Verilog code examples thorougly, you should notice that the bit width field of sized constants usually matches the target size.  regSysDX <=# tDLY 4'h0; would be a matching assignment. Generally, the compiler also accepts unsized constants as in your second example, but you will get a warning then, if it isn't disabled. By the way, the# tDLY is ignored in synthesis, it's functional in ModelSim only,

[Altera_Forum]

how can i fix it? please give me a solution

[Altera_Forum]

What co you mean? I suggested to use sized constants of correct size and gave an example.  

 For general questions regarding verilog syntax, I suggest to consult a Verilog manual or textbook.http://www.stanford.edu/class/ee108b/labs/verilog_reference.pdf