Setup an IRQ on a component

[Altera_Forum]

Hi ,  

 I made a "counter" component which I want to interrupt NIOS when reaching 8'h7. I also created a control register in which is bit IRDY (Interrupt Ready)   I have 2 questions for my component :   1) How can I setup an IRQ for it ?  ( like UART , its IRQ is 5. This info is in "System Contents" tab of "Altera SOPC Builder" )  2) How can I make NIOS "connect" with my IRDY bit ?  Thank you so much ,  Quan

[Altera_Forum]

Hi, 

you have to use the "create new component" tool in SOPC builder: insert your HDL file in the "HDL files"page and then specify your pins function in the "signals" page, nad in your case your interupt pin. Before you had to define your interupt as an output pin of your HDL component.  bye

[Altera_Forum]

--- Quote Start ---  originally posted by soin@Sep 19 2006, 05:12 PM hi, you have to use the "create new component" tool in sopc builder: insert your hdl file in the "hdl files"page and then specify your pins function in the "signals" page, nad in your case your interupt pin. before you had to define your interupt as an output pin of your hdl component.  bye <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18337)  --- quote end ---    --- Quote End ---    Hi Soin,  I already added my counter component to SOPC Builder. Here is the wrapper which instantiates the task logic of counter and its interface (defining control , status , ... registers) :   module counter_avalon_interface (  clk , // global signal , clk , 1bit , input  reset_n , // global signal , reset , 1bit , input  chipselect , // avalon_slave 0 , chipselect , 1bit , input  address , // avalon_slave_0 , address , 2bit , input  write , // avalon_slave_0 , write , 1bit , input  writedata , // avalon_slave_0 , writedata , 8bit , input  read , // avalon_slave_0 , read , 1bit , input  readdata , // avalon_slave_0 , writedata , 8bit , output     counter_out, // avalon_slave_0 , writedata , 8bit , export  intr // avalon_slave_0 , writedata , 1bit , export ????? );  I also assigned counter_out to LED&#39;s but I am not sure of :   1) what pin I should assign intr to make CPU interrupted when it is high.  2) What I should do with my component to make it CPU-interruptable like UART , PIO , ....  Have you got ideas about this ?  Regards,  Quan

[Altera_Forum]

Hi Soin, 

 Thank you very much for your tips. I did it!!!  I almost forgot irq pin in signal tab of component editor.  Thanks,  Quan

[Altera_Forum]

Hello ,  

 I map the signals as following :   module counter_avalon_interface ( clk , // global signal , clk , 1bit , input reset_n , // global signal , reset , 1bit , input chipselect , // avalon_slave 0 , chipselect , 1bit , input address , // avalon_slave_0 , address , 2bit , input write , // avalon_slave_0 , write , 1bit , input writedata , // avalon_slave_0 , writedata , 8bit , input read , // avalon_slave_0 , read , 1bit , input readdata , // avalon_slave_0 , writedata , 8bit , output   counter_out, // avalon_slave_0 , writedata , 8bit , export intr // avalon_slave_0 , irq , 1bit  );  and use this code in NIOS IDE to "process" the interrupt :  # include <stdio.h># include <sys/alt_irq.h># include <io.h> # include "counter_routines.h"# include "system.h"# include "altera_avalon_uart_regs.h"  void counter_isr( int context );  int main() {  int context = 0;    printf("Hello from Nios II!\n");    SetInterrupt( COUNTER_0_BASE ); // enable IRDY , my own HAL driver    alt_irq_register( COUNTER_0_IRQ , &context , counter_isr );     while( 1 )  {  }   return 0; }  void counter_isr( int context ) {  // output &#39;Y&#39; to UART   IOWR_ALTERA_AVALON_UART_TXDATA( UART1_BASE , &#39;Y&#39; ); }  -------   It seemed that CPU wasn&#39;t interrupted.  Anybody has got this issue before ?  Thanks,  Quan

[Altera_Forum]

Hi, 

are you sure your component generate interupt?is your uart working well?You could try to set a variable, checking it in the main loop, and printf through uart-jtag or uart, using the HAL library instead of writing register...

[Altera_Forum]

--- Quote Start ---  originally posted by soin@Sep 20 2006, 02:29 PM hi, are you sure your component generate interupt?is your uart working well?you could try to set a variable, checking it in the main loop, and printf through uart-jtag or uart, using the hal library instead of writing register... <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18357)  --- quote end ---    --- Quote End ---    Hi Soin,  > are you sure your component generate interupt?# ## Yes , I am. I checked intr pin. It does go high whenever the counter reaches 7.  > is your uart working well?You could try to set a variable, checking it in the main loop, and printf through uart-jtag or uart, using the HAL library instead of writing register...# ## Yes , my UART is working well. I tested it in a seperate project by using this function in HAL library :  IOWR_ALTERA_AVALON_UART_TXDATA( UART1_BASE , &#39;Y&#39; );  After testing these stuff , I assign intr pin to irq in component editor , signal tab ; then recompile the System , Quartus project and NIOS IDE program but things are not better.  Have I got some steps missed ?   Thank you ,  Quan

[Altera_Forum]

Hi, 

How long does your interupt signal stay high?Nios interupt is level sensitive, so maybe your interupt signal is too short and the processor doesn&#39;t detect the interupt.In general your peripheral should assert interupt pin, and it should stay high (or low) as long as the Nios acknoledges the interupt, for example writing a bit in a peripheral&#39;s register .It&#39;s only an idea... bye

[Altera_Forum]

--- Quote Start ---  originally posted by soin@Sep 21 2006, 03:31 PM hi, how long does your interupt signal stay high?nios interupt is level sensitive, so maybe your interupt signal is too short and the processor doesn&#39;t detect the interupt.in general your peripheral should assert interupt pin, and it should stay high (or low) as long as the nios acknoledges the interupt, for example writing a bit in a peripheral&#39;s register .it&#39;s only an idea... bye <div align='right'><{post_snapback}> (index.php?act=findpost&pid=18374)  --- quote end ---    --- Quote End ---    Hi Soin,  My interrupt signal stays high in 1 clock.  How do I know NIOS acknowledges the interrupt ? Have you got any documents discussing about these (the "lenghth" of interrupt signal and NIOS interrupt acknowledgement) ?  Thank you,  Quan

[Altera_Forum]

Hi Soin , 

 I did it !!! As you guess , my interrupt signal is too short for NIOS to recognize. I made it long until NIOS receives IRQ and processes ISR in which I de-activate the interrupt signal.  Now it really works!!!!  Thank you very much, Soin  Quan

[Altera_Forum]

Hi quan 

 Can you send me your source??  Thanks

[Altera_Forum]

@Soin  

Currently I'm trying to put an interrupt in my custom component. I have one question, in the interrupt signal (in my case its type is 'interrupt sender') properties, which Avalon MM that I suppose to assign? I still confused with the 'associateAddressablePoint' meaning... :( Could you explain it to me? I've tried to provide an Avalon MM slave consists of a 'write' and a 'writedata' signal. This Avalaon MM slave function is to let the CPU send a command to clear the interrupt bit. Then, I assign my interrupt signal in SOPC to this Avalon MM. However, the result is very strange... my program totally doesn't work, even it has hanged in the beginning.... :(   Help me..please...

[Altera_Forum]

I don't really know what this setting is used for, but I always associate the interrupt sender to the MM interface used to clear the IRQ bit too, and never ran into any problem. 

Your problem has probably another explanation. You could use SignalTap to check the status of you IRQ, see if it raised and check that it is properly cleared by the interrupt handler.

[Altera_Forum]

Hi everyone. I am also designing an counter with interrupt. This is my code: 

//Write 1 to address 0 to start counter //Write 2 to address 0 to stop counter //Write 0 to address 0 to reset counter //Read address 1 to get count value module counter (clk, reset, address, chipselect, read, readdata, write, writedata,irq); input clk, reset, chipselect, read, write; input address; input writedata; output readdata; output irq; reg readdata; reg count; reg control; reg irq; //wire done; always @ (posedge clk) begin if (control==2'b01) count <= count + 1; else if (control==2'b00) count <= 0; else count <= count; end //assign irq=(count==32'd10)?1:0; always @ (posedge clk) begin if (count>=32'd1000000000) irq<=1; else irq<=0; end always @ (posedge clk) begin if (chipselect && write && (address==0)) control <= writedata; else if (chipselect && read && (address==1)) readdata <= count; else if (!chipselect) readdata <= 32'hZ; end endmodule   And this code functions perfectly as wanted. But when want to add custom hardware in SOPC having trouble to select the interface and signal type. It shows an error Associated Addresablepoint out of range. :cry: Is it correct how i design the counter with interrupt? and how to add to SOPC builder? Any suggestions please. Thank you.

[Altera_Forum]

Hi Moganesh, 

 As Daixiwen said, to establish the interrupt in your component, besides providing interrupt signal, you also have to provide a register to store the IRQ state. Then in the interrupt signal properties, just associate the avalon MM to this register.  I'm sorry I couldn't send the component file to you, because currently I can't access my workstation.  Good luck

[Altera_Forum]

Hi fightingdreamer, 

 I did what you told like creating a register to store the interrupt and associated avalon mm slave to the register but still having the problem  Here is the C-code:  //Write 1 to address 0 to start counter //Write 2 to address 0 to stop counter //Write 0 to address 0 to reset counter //Read address 1 to get count value module counter ( //Avalon MM clk, reset, address, chipselect, read, readdata, write, writedata, //Interrupt_handler irq,readdata_irq,writedata_irq,write_irq); input clk, reset, chipselect, read, write ; input write_irq ; input address; input writedata; output readdata; output irq; input writedata_irq; output readdata_irq; reg readdata; reg count; reg control; reg readdata_irq; reg irq; //wire irq; always @ (posedge clk) begin if (control==2'b01) count <= count + 1; else if (control==2'b00) count <= 0; else count <= count; end //assign irq=(count==32'd1000000000)?1:0; always @ (posedge clk) begin if (count>=32'd1000000000) irq<=1; else irq<=0; end always @( posedge clk) begin if (irq) begin readdata_irq<=1; end else if (write_irq && writedata_irq) begin readdata_irq<=0; end else readdata_irq<=0; end always @ (posedge clk) begin if (chipselect && write && (address==0)) control <= writedata; else if (chipselect && read && (address==1)) readdata <= count; else if (!chipselect) readdata <= 32'hZ; end endmodule   I still having problem with the error showing Associated Addresablepoint out of range.

[Altera_Forum]

Hi, 

 Actually just now i did not set the associated addressable interface parameter of the interrupt sender. That is what causing the errors. But I still having warning as follows:   Warning: counter_0.irq: Interface has no signals Warning: counter_0.irq: Master has no read or write interface Warning: counter_0.interrupt_handler: readdata width must be in {8, 16, 32, 64, 128, 256, 512, 1024} for dynamic addressing Warning: counter_0.interrupt_handler: writedata width must be in {8, 16, 32, 64, 128, 256, 512, 1024} for dynamic addressing   Is the warning have to be considered or can be ignored?

[Altera_Forum]

Those warnings are rather strange. The first seems to say you didn't declare any signal in the irq interfare. Don't you have at least an irq signal? The second one seems to indicate that your irq interface is an Avalon master rather than an interrupt sender. 

For the two others, your data bus should really be with a size that is a multiple of 8, even if you read/write only one bit.

[Altera_Forum]

Your data bus really needs to be 32bits for accesses from a NiosII cpu. 

Otherwsie a 'bus width adapter' will be added to convert the 23bit master cycle from the Nios into multiple slave cycles (with the appropriate byte enables for writes).