Emulation and writing drivers

[Altera_Forum]

Hi all, 

Once I designed an FIR and loaded it into the FPGA. I want to write drivers to input data to this FIR (which is in now on the FPGA) and read back the output and verifi the output. Can anyone please explain me the procedure to do this or point me to some tutorial/document.   I know how to write a driver to those components SOPC compatible. However, my FIR cannot be instantiated in SOPC builder. How can I read and write to this piece of hardware? Do I need register mapping and stuff??   Thank You

[Altera_Forum]

Are you using the FIR compiler from Altera or your own FIR?

[Altera_Forum]

I am using my own fir. I wrote my own verilog code. I think the FIR compiler from Altera is a megacore IP and it is SOPC compatible, am I write?

[Altera_Forum]

If you're using the NIOS processor, you basically write a AVALON slave device with the memory mapped registers you require, then instantiate it with exported signals that directly drive the FIR you designed.  

 If you are using some external CPU, then you would have to do the same thing, except it would more likely be an EMIF, AMBA, or some other interface.  The Avalon bus is fairly strait forward and can be found here:  www.altera.com/literature/manual/mnl_avalon_spec.pdf  SOPC Builder has a wizard that allows will read this slave device verilog, and assign the AVALON and non-avalon signals. For signals that would be directly connected to your FIR, you would assign these as EXPORT, and they will show up in the top level of the design. This is where you would instantiate the FIR filter as well, manually assign the ports.  If you want the data path for the FIR to come from and go to system memory, and not just the setup, you probably want a both a Avalon Master and and Avalon Slave device that hooks it up.  Here it's a little more complex, and but basically the same idea. If you ware writing a master device however, be careful on memory boundaries if using bursting. The Avalon bus doesn't currently recognize memory burst boundaries, and will give you out of order data in some cases.    Pete

[Altera_Forum]

The great thing about FPGAs is you can pretty much create anything you want (in this case where you have your own FIR). Its probably going to be dictated by the format of where the data is coming from.

[Altera_Forum]

Hi guys thanks for the help. That document is help full. I also found a tutorial on how to build a SOPC component. Will be help full in future ref. 

Quartus II Handbook Volume 4: SOPC Builder  Chapter 9. Developing Components for SOPC Builder (ver 7.2.1, Oct 2007, 347 KB)  Design Example   http://altera.com/literature/hb/qts/qts_qii54007.pdf