FIR, Dual clock FIFO and FIR integration synthesize doubts...

[Altera_Forum]

Hi, everyone, 

 I am using Quartus II 9.0 sp2.  I am connecting two FIRs together, between which I have put a Dual-Clock FIFO because those two FIRs are operating in different clock domains.  I used SOPC builder to connect them. I have tried to use different clocks for FIRs by changing the clock values inside SOPC builder.  e.g. First, I used 50MHz for the first FIR and 100MHz for the second FIR; for the second time, I used 50MHz and 51MHz for the second FIR.  Theoretically, the second case should cause much more complicated system than the first one as there will be much more state machines at their interfaces in order to prevent data loss and so on.  However, to my surprise, after synthesizing these two designs, I have found that the NO. of registers, pins, memory bits used and the power consumption never changed.  Why is it like this?  Thank you very much grit

[Altera_Forum]

any one has any clue..?? or need more information???  

 really need help... thank you =)

[Altera_Forum]

I can't follow your assumption, that there should be a difference between both variants, if you use a FIFO. A 100 MHz data sink can possibly connect to a 50 MHz data source without a FIFO, if the clocks are supplied from a PLL with suitable phase. But with a FIFO, only maximum speed has to be kept.

[Altera_Forum]

--- Quote Start ---  I can't follow your assumption, that there should be a difference between both variants, if you use a FIFO. A 100 MHz data sink can possibly connect to a 50 MHz data source without a FIFO, if the clocks are supplied from a PLL with suitable phase. But with a FIFO, only maximum speed has to be kept.  --- Quote End ---    Hi, thanks a lot for the reply.  Because I used SOPC builder to connect these two FIRs. The Dual-Clock FIFO is a must as the Avalon ST interface can only be used when the two ports (source data and sink data) have the same clock domains.  I suppose the Avalon ST interface will be different for different combination of clocks? Or is it? e.g. for 51Mhz is interfaced to 50Mhz, it is supposed to be more complicated to avoid the data loss? Or my understanding is completely wrong?  By the way, I didn't use PLL, the clock is external clock.  Thanks!

[Altera_Forum]

If you were to design your own FIFO, *maybe* (and I'm too tired to think properly about this parte) you could come up with a simpler design for a 50/100 MHz case than for a 50/51 MHz case. 

 However, the DC FIFO component assumes nothing about your clocks and always generates a generic component that will *always* work, no matter the case.  So, you get the same logic usage for both cases. Of course, if you're using timming driven synthesis you may (or not) see small differences.

[Altera_Forum]

--- Quote Start ---  If you were to design your own FIFO, *maybe* (and I'm too tired to think properly about this parte) you could come up with a simpler design for a 50/100 MHz case than for a 50/51 MHz case.  However, the DC FIFO component assumes nothing about your clocks and always generates a generic component that will *always* work, no matter the case.  So, you get the same logic usage for both cases. Of course, if you're using timming driven synthesis you may (or not) see small differences.  --- Quote End ---    Hi, thanks a lot for the explanation. Then there must be situations when the FIFO cannot guarantee no data loss, right? Do you have any idea what are those cases? I can't really find much useful information from the DC FIFO user guide downloaded from altera website..  thank you

[Altera_Forum]

No, there are no deterministic cases that will cause the DC FIFO to fail (except if you try to read from an empty FIFO or write to a full FIFO). 

 There are stochastic conditions that can cause metastability.  You can't do much to avoid them, you can just increase the number of synchronization stages to reduce the probability of a failure to an aceptable level.

[Altera_Forum]

--- Quote Start ---  No, there are no deterministic cases that will cause the DC FIFO to fail (except if you try to read from an empty FIFO or write to a full FIFO).  There are stochastic conditions that can cause metastability.  You can't do much to avoid them, you can just increase the number of synchronization stages to reduce the probability of a failure to an aceptable level.  --- Quote End ---    Hi, do you know where I can find some more details about the Dual Clock FIFO? Like how it works, the internal connection, the specification and so forth?  The altera document is too abstract and information limited..  Thank you so much!

[Altera_Forum]

This is the only documentation I know of 

 http://www.altera.com/literature/hb/nios2/qts_qii55014.pdf http://www.altera.com/literature/ug/ug_fifo.pdf