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i use DDR hp controller to interface a micron ddr chip mt46v32m16, two chips to form 32bit width.
but when i send out read request and wait the read data and read data valid sinal, they come back , but not aligned, local_rdata_valid is 11 clocks later tham local_rdata, how can that happen? anybody knew this issue?/Link Copied
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I encountered the same question as you. Hope someone can solve it !
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hi, there,
i have solved my problem, it just need a longer time reset, for example 200ms, on my board, i think this is caused by my Vref dc-dc chip don't output right when i download my new sof file for a while. hope useful for u!
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