Dual-Port Ram Implementation Questons

[Altera_Forum]

Hello everybody! 

 I need to use a Ram block in my project, and I have been experimenting with the Mega-Wizard to implement a Dual-Port Ram block, using M4K On-Chip Memory Blocks.  I have read/studied chapter 7 of the Altera Cyclone Handbook, but there are still a few points I need to clear out.  1) Regarding "aclr" (clear/reset of RAM), I need to implement it Active Low, but I couldn't find such an option. I thought of putting a NOT at the input signal of the Ram Block, but because of Wizard-generated code I'm not sure if this a good idea.  2) I saw that I can specify different data input and output widths, e.g. I need a 16-bit input and an 8-bit output. I couldn't find any description of how this works. Is data outputted serially? Are there any suggestions referring to this?  Thank you in advance!

[Altera_Forum]

1) don't edit the MegaWizard code to add an inverter, just add it to your code that controls the RAM (or between the RAM and its controller) 

 2) with a RAM alone its up to you how to use each of the mixed width ports. the DCFIFO user guide has an example of what a dual clock mixed width FIFO write/read looks like on page 18:  http://www.altera.com/literature/ug/ug_fifo.pdf

[Altera_Forum]

1. Why do you need it to be active low? just invert the signal at the input in your design file (not the megawizard output file). But I would recommend not using aclr at all if you can avoid it because of the problems it can bring. What are you using the memory for? 

 2. All that happens is that it changes the number of address bits on each side. for you, if you had a 16x256 memory on side A (8 address bits) you would have 8x512 on side B (9 address bits).

[Altera_Forum]

1) Ok, I simply put a NOT gate at the schematic, before the signal being input to aclr. 

 I use an asynchronous reset throughout whole the system, which is active low, that's why I needed it to be the same - so I can assign it the same reset-signal.  The Ram Block is used for buffering raw 16-bit audio samples, which are then encapsulated into UDP packets. Obviously there will be no problem at all if I didn't use aclr. I didn't know about it causing troubles.   2) Actually, because of the Eth_TxD code I'm using, I need to get these 16-bit samples in 8-bit pieces at the output, but with the MSB first (?!). I got that with the addresses, and I can also clock it elsehow if I want/need to. Does it start with the MSB of the word stored?  I have actually achieved that, but in a less professional way (leaving available the 16-bit output data for twice a time, so I can retrieve the same sample/word twice - e.g. RamOut(15 downto 8) first and then the rest, and so on..), so I'd like to make it look better.  Thank You.

[Altera_Forum]

Ok, I tried out the different widths in the Ram Block, and it was too easy to be true. 

My initial thought was correct, DATA is retrieved inversely - LSB first. That means, that the 16-bit words written in, are read out as 8-bit words, with the LSB of the Sample first.  Any ideas how to correct that?  Thank you.

[Altera_Forum]

swap all the connections on the data side. You can connect any of the 16 bits on the input to any bit in the memory. They dont have to connect in any particular order.

[Altera_Forum]

Please specify your answer a little bit more, if possible. 

What exactly do you mean by swapping the connections on the data side? Thank you.

[Altera_Forum]

in the same way you connected a not gate to the reset input, you can map any incoming bit to any data bit. So the LSB could become bit 2 in the memory if you wanted it to. All you have to do is connect bit(0) of data to bit(2) of the memory D. If you really wanted you could map the reset into the memory too. FPGAs are very flexible about things like this.

[Altera_Forum]

Ok Tricky sorry to bother you again, but I can't find how to do this. Is that done at the schematic? Do I have to use some kind of multiplexer? Thanks again.

[Altera_Forum]

Yes that is done in the schematic (assuming you're using the Quartus schematic entry tool. 

 You cannot connect the links directly, you have to use named nets. I think there is a "group" block so you can regroup busses.  All of this is MUCH easier in VHDL or verilog. Its a bit tedious in schematic.

[Altera_Forum]

Ok, you were right, didn't find anything in schematic at all! 

 I tried changing it in the VHDL created top-entity port map file, in quite an easy way. I split the incoming DATA into two SYNTHESIZED_WIRES, (15 downto 8) and (7 downto 0), and then matched them to the data_bus of the ram block, firstly with concatenation, and then seperately. Unfortunately neither of what I tried showed any result, as in simulation data is still read inversely.  What else can I try? I appreciate your help!

[Altera_Forum]

but did you do this? 

 data_bus(7 downto 0) <= DATA_IN(15 downto 8); data_bus(15 downto 8) <= DATA_IN(7 downto 0);  or you can just do it directly:  data_bus(0) <= DATA_IN(7); data_bus(1) <= DATA_IN(6); data_bus(2) <= DATA_IN(5); data_bus(3) <= DATA_IN(4); ...etc

[Altera_Forum]

Tricky thank you and sorry about not answering. 

I finally solved it out in a much easier way: I just change the MSByte (!!) with the LSByte in another block of my design (where DATA is actually 'created')! I was stuck in the idea of solving it either at the Ram block or at the generated port-map block. Anyway..  Thanks again for your interest!