Altera feature downgrades w/ 10.x

[Altera_Forum]

As of 10.x, The easy-to-learn and use native Quartus simulator is gone--poof! 

 Rumors abound that .bdl designs, gates & primitives, and legacy logic module support are soon to be axed--poof!  I'll share a bit of recent discussion w/ another engineer: ----------- Well, I talked with {local Altera distro rep) this very AM, and he hemmed and hawed to the effect that a .bdl design must be exported as a Verilog or VHDL digest, which can then be handled with Modelsim. So while schemata, legacy blocks, and primitives seem to be supported--for now--they have to be double-clutched through HDL synthesis; more time, bother & expense.  {rep} maintains that "practically nobody" was using the Quartus native simulator anyway, and so it ultimately failed to make the cut in product development resources. He's probably right, with half-million line HDL code and licensed IP projects dominating lucrative high-density FPGA deployments. Altera has made the message clear: pikers like us who design-in small CPLDs with low volumes can take a hike.  Well, I and the other "practical nobodies" out in the real world have one more reason to consider other programmable logic vendors. If "everybody" is really using Modelsim or other 3rd-party HDL-based simulators, then what makes Altera so special anymore? Why should anybody remain loyal to them after being %#$@! once or twice?  The %#$@!s in Altera who got bonuses for axing the simulator overlooked the most obvious unintended consequence, namely that once everything has been stuffed into HDLs and Modelsim suites, vendor lock disappears: with transportable HDL designs, any FPGA vendor can provide the silicon now.  Thus, I feel free to revisit Xilinx to see what they've got. X got arrogant for a while, but if I'm gonna relearn a simulator it might just as well be theirs. Lessee, Avnet and digikey are the two distros; pity {rep's employer: major semi distro} does not seem to handle them. Huh.  The only bones {rep} could throw my way was a Modelsim training link (search for ODSW1120) and a kind offer to drop by & get me started in the brave new world of Modelsim.  Maybe {rep} would care to sum up just what we can expect from dear old Altera in future? For the first time in 15 years I am now reluctant to specify Altera for new projects, whether I work for a dinky outfit like {small company}, or a $billion company like {major name-brand company}.  //{atemp99} aka Nobody EE.  PS As a hardcore hardware EE, with the odd exception of handiness in state machines, I hate HDLs.:mad: Too much like the s-word (software).

[Altera_Forum]

--- Quote Start ---   The %#$@!s in Altera who got bonuses for axing the simulator overlooked the most obvious unintended consequence, namely that once everything has been stuffed into HDLs and Modelsim suites, vendor lock disappears: with transportable HDL designs, any FPGA vendor can provide the silicon now.  Thus, I feel free to revisit Xilinx to see what they've got. X got arrogant for a while, but if I'm gonna relearn a simulator it might just as well be theirs.  --- Quote End ---   You do have valid points there. The distinguishing reason why I switched from Xilinx to Altera was superior off-the-shelf design entry tools. That doesn't mean that some other existing developer of huge (profitable) designs is going to switch because of some entry-level design tools; but it does mean that if you take away the off-the-shelf design entry tools, the chances a rookie developer will start using Altera (and then stick with it for the rest of his career) are getting very slim indeed.  It levels the playing-field, and therefore decreases vendor lock-in (which is good for the market/competition, but bad for Altera in this case, since they lose one of the few edges they had).

[Altera_Forum]

--- Quote Start ---  ... if you take away the off-the-shelf design entry tools, the chances a rookie developer will start using Altera (and then stick with it for the rest of his career) are getting very slim indeed.  It levels the playing-field, and therefore decreases vendor lock-in (which is good for the market/competition, but bad for Altera in this case, since they lose one of the few edges they had).  --- Quote End ---    So-called entry-level tools are actually quite fine for even mid-sized projects by experienced engineers, which is why I miss the basic Quartus simulator: it's a good-enough-thank-you aid for incrementally-built designs. I neither need nor want a hugely-capable simulator that takes an entire dedicated, separate design effort, slowing me down and making me less productive.  Altera really screwed the pooch in discontinuing the native sim. If Xilinx's competitive tools didn't s*ck so bad Altera's position would be even more precarious.  //atemp99

[Altera_Forum]

--- Quote Start ---  So-called entry-level tools are actually quite fine for even mid-sized projects by experienced engineers, which is why I miss the basic Quartus simulator: it's a good-enough-thank-you aid for incrementally-built designs  --- Quote End ---   That's precisely the way I use(d) it (on a 4000 LUT design), so I feel your pain, yes.

[Altera_Forum]

atemp99, 

 "poof"...really? Altera's been making people aware that this is going away for years now. All your other points (some quite valid) aside, surprise should certainly not be one of your sentiments.  slacker

[Altera_Forum]

Another important thing to remember is that with the demise of the native simulator, it is now impossible to functionaly simulate AHDL code. Fine, you say... just use verilog - problem is, I've been using AHDL exclucively ever since the early days of Max+II, when it was the language Altera encouraged everyone to learn. It works just fine for me, I've got an entire career's worth of AHDL in the bank, and now I am simply totally and completly f*&*ed by Altera if I want to ever use the new tools with my existing library of AHDL routines. Thanks a lot, Altera - 

 -Your once loyal customer-

[Altera_Forum]

--- Quote Start ---  "poof"...really? Altera's been making people aware that this is going away for years now. ... surprise should certainly not be one of your sentiments.  --- Quote End ---   I did hardware design in 1983-1989, software design 1980-now (Linux kernel development, GCC compiler design, amongst other things); so forgive my ignorance (and surprise) as I parachuted into FPGA design since June 2010 only to find that the hardware design world seems to have evolved in dubious ways in the past 21 years (given the progress that I've been part of in the software world).

[Altera_Forum]

ASIC design practices (using HDL coupled with SDC timing constraints) must be used on the high end of Altera's offerings and, I'd gather, that this is what drives them throughout their tools. 

 As to whether or not the issues you're all presenting are real, they are...but...they're not "just" Altera's issues. IMHO, the entire EDA industry has not really had any significant innovation (http://www.sigasi.com/content/latest-eda-innovation-logic-synthesis) since logic synthesis in the early 90s.  Incidentally, the author is the creator of a nice little HDL tool called myhdl (http://www.myhdl.org/) (Python-based HDL) and his 'blog (http://www.sigasi.com/janhdl) always makes for interesting reading.  Regards,  slacker

[Altera_Forum]

--- Quote Start ---  "poof"...really? Altera's been making people aware that this is going away for years now. All your other points (some quite valid) aside, surprise should certainly not be one of your sentiments.  --- Quote End ---    Uh huh, like I have nothing better to do than keep up with Altera press releases and their slow frog boil.  Like other HW engineers who do more than "code monkey" design, my CPLD/FPGA design load may vary between 0% and 100% on an inconsistent basis, depending on client needs and my design judgment. I might go months/years without using a tool, so when, as with Quartus 10.x, I revisit it several versions later than the last time, the cumulative deltas become quite apparent.  So I'll hold onto my reaction (disgust, now), thanks, and maintain my conclusion that Altera Quartus II v10.x has been castrated, downgraded, stripped of valuable and valued resources and features, and repositioned as just another d*ckwad HDL suite, suitable only for postmodern code-primates who evidently believe that anything non-Verilog lies in the realm of Stone Knives and Bearskins, and to whom Markus looks like hieroglyphics. So sad. Eye, emm, oh.  Guess I'll go fire up PALASM and maybe that newfangled ABEL. ;)

[Altera_Forum]

haven't looked into this yet but it sounds good. 

 jack  improved simulation experience  New ModelSim-Altera Edition and ModelSim-Altera Starter Edition version 6.6c deliver a new waveform editing capability. When you're working on a part of your design, you can use waveform editing to quickly generate input stimulus for verification by editing a waveform instead of spending your time developing a testbench. Version 6.6c of the software tool also delivers new operating system (OS) support, including Windows 7 and SUSE Linux 11.

[Altera_Forum]

--- Quote Start ---  haven't looked into this yet but it sounds good.  jack  improved simulation experience  New ModelSim-Altera Edition and ModelSim-Altera Starter Edition version 6.6c deliver a new waveform editing capability. When you're working on a part of your design, you can use waveform editing to quickly generate input stimulus for verification by editing a waveform instead of spending your time developing a testbench. Version 6.6c of the software tool also delivers new operating system (OS) support, including Windows 7 and SUSE Linux 11.  --- Quote End ---   I had the same feeling as stated above, but after a day of using this "new" feature in modelsim, "editing a waveform" , I could simulate in no time just like with the altera simulator. Just read chapter 12 of the modelsim user manual. I still have a problem about how to simulate schematic entry type designs with modelsim or simulating mixed verilog/schematic designs with modelsim.

[Altera_Forum]

I think that Altera, dismissing proprietary simulator and timing analyzer and completely adhering to Modelsim simulation, Synopsis design Constraint and TimeQuest Analyzer, allows the designers to move easily towards other FPGA vendors. 

 This is indeed a good point for us.   Further, this is a proof that Altera feels that their devices have equal (if not better) price/performance ratio with respect to the competitors.   Maybe difficult to slightly change our design habits at the beginning. But I think that at the end we'll get better devices and greater design flexibility.   IMHO.

[Altera_Forum]

I do not understand why you people (the ones that use/want the Altera simulator) do not just use QuartusII 9.0sp2 and be happy ? 

 I want to use systemVerilog, I want new language features, I want a better Qsys and stuff like that, so I need the latest and greatest version.  But you guys, you guys seam to only want madure features that are already available in 9.0sp2, so why don't you keep that ??  Anyone care to comment ?

[Altera_Forum]

--- Quote Start ---  I do not understand why you people (the ones that use/want the Altera simulator) do not just use QuartusII 9.0sp2 and be happy ?  I want to use systemVerilog, I want new language features, I want a better Qsys and stuff like that, so I need the latest and greatest version.  But you guys, you guys seam to only want madure features that are already available in 9.0sp2, so why don't you keep that ??  Anyone care to comment ?  --- Quote End ---   That's exactly what I'm doing. I develop and test my building blocks with QuartusII 9.1sp2 using the internal simulator. But for a new HW we will use Cyclone IV, so QII 10.1 will be necessary to close the timing. But I never simulate a top-level project anyway, I can debug that easily by writing test-SW and take a good look at what happens or as a last resort use signaltap.  Just like you I'd like to use the new features in VHDL 2008, in my case, but that doesn't mean we have to give up a good thing as the user interface of the internal simulator. We had that discussion in another thread already. It would have been great if the user interface had stayed, whatever program is running the simulation we don't care about, but we're all hooked on the simplicity to test 'small' building blocks we then later use in 'big(ger)' designs. The waveform editing in ModelSim version coming with QuartusII 10.1 may be a possibility, it looks that is all we're going to get, but we have to learn how it works. Ppitou gives us good hopes though. The new work-flow is geared towards the 'big' organisations with large teams, and very possibly Altera is targeting to lure Xilinx customers over. This imposed design flow also makes it easier for us to look at other devices (from competitors). So I agree with nplttr, we will loose some time adjusting to the new tools, but eventually we will use them.

[Altera_Forum]

A few things of note: 

1) The entire GUI was basically re-written in Q10.0. So it wasn't like the simulator's existing code was dropped. Instead it was decided to not spend a lot of time re-building this GUI-intensive feature.  2) Being an internal simulator, every model is custom built, i.e. it's not an HDL simulator(which is what you like about it). Each generation of devices has new/changing features, DLLs and DQS strobes for DDR, dedicated SERDES with DPA and CDR, transceivers, hard PCI Express cores, etc. These are hard enough to maintain for VHDL/Verilog simulators, but to throw in another hand-built model and verify is not a simple task. I'm guessing that's one of the major reasons. And you could argue that they should just not use this simulator for the high-end stuff, but all these high-end features are trickling down to the low end devices. Cyclone with high-speed transceivers, for example. I liked the simulator quite a bit too, for the reason of being able to simulate some small piece of code in about 2 minutes. As soon as something got more complex than that(and they often do), I regret having started down that path. I wish item 1) weren't an issue, in which case the simulator could have been left as is, and slowly die as it didn't support new features.  I'm sure Altera is fully aware this allows designers who would have been 100% faithful to Altera tools to now look around. I think my only point is that it's a lot more complicated than they just dropped a feature for the heck of it, not that anyone said that's what happened...

[Altera_Forum]

--- Quote Start ---  A few things of note: 1) The entire GUI was basically re-written in Q10.0. So it wasn't like the simulator's existing code was dropped. Instead it was decided to not spend a lot of time re-building this GUI-intensive feature.  2) Being an internal simulator, every model is custom built, i.e. it's not an HDL simulator(which is what you like about it). Each generation of devices has new/changing features, DLLs and DQS strobes for DDR, dedicated SERDES with DPA and CDR, transceivers, hard PCI Express cores, etc. These are hard enough to maintain for VHDL/Verilog simulators, but to throw in another hand-built model and verify is not a simple task. I'm guessing that's one of the major reasons. And you could argue that they should just not use this simulator for the high-end stuff, but all these high-end features are trickling down to the low end devices. Cyclone with high-speed transceivers, for example. I liked the simulator quite a bit too, for the reason of being able to simulate some small piece of code in about 2 minutes. As soon as something got more complex than that(and they often do), I regret having started down that path. I wish item 1) weren't an issue, in which case the simulator could have been left as is, and slowly die as it didn't support new features.  I'm sure Altera is fully aware this allows designers who would have been 100% faithful to Altera tools to now look around. I think my only point is that it's a lot more complicated than they just dropped a feature for the heck of it, not that anyone said that's what happened...  --- Quote End ---    1. We often hear, if it ain't broke don't fix it ... and not everything works flawlessly in 10.0 and 10.1 either. Not re-building the simulator GUI ultimately meant dropping it, no? 2. It is not the HDL simulator we like, but the User Interface of being able to draw waveforms instead of writing dozens of processes and adding up times. Now it looks like we can edit waveforms in ModelSim itself, so we will stop moaning (after a while ...). On your reasoning : if you start something small and it grows beyond what the internal simulator / waveform editing can handle, you should think before you leap (I'm quite convinced you always do that ...).  I hope we can stop this discussion soon now. It is clear Altera will not put the internal simulator GUI back (being too much work as you say, which ultimately was nothing else then a bottom-line decision).

[Altera_Forum]

At the end of the day, here's what it boils down to: 

• you have to learn to use another tool (Modelsim) and all it's peculiarities and special incantations 
• you can no longer simulate ahdl or mixed vhdl / verilog designs behaviorally 
• there is a bigger "fixed cost" with making any design, as you have to build a test bench.
• This is a killer in small designs, but definitely saves time in bigger designs, as the modelsim simulator runs a lot faster and has some clever debug capabilities (that take time to learn). Also, when doing things like bus-based designs, these languages allow you to create procedures or tasks to do bus-writes or bus-reads, which allows you to set up PLD-based peripherals and registers a lot faster. 

  My guess from all this is that AHDL is going to disappear. VHDL and Verilog are very different languages from AHDL, and are, sadly, significantly more verbose. I've been making the transition from AHDL to Verilog and now to VHDL for the last two to three years and it has been challenging.  I do moderate complexity PLD designs in support of PCB design, so I do a burst of PLD design activity for a while, then very little for months at a time. Whereas AHDL is a very literal text description of hardware, well written VHDL or Verilog is not. If you're used to laying out literal hardware blocks in your head - like I was - it will take you a while to make the paradigm shift to these languages.  The real catch is that each of these languages is actually TWO languages: a behavioral/simulation language and a hardware-description language. I'm OK with the hardware design side, but still haven't quite gotten all the subtleties of creating clean and transportable test benches.  It does seem like Altera is abandoning the low-end of PLD design in favor of supporting large customers doing large team-based designs. An end of an era.

[Altera_Forum]

It was brought up on an earlier post in this thread that the user had a lot of AHDL and couldn't use it any more. The way AHDL/Schematics used to be simulated was by running quartus_map and then running the simulator. (There was a "Generate Functional Simulation", which just ran quartus_map, maybe with some options to make it quickly). To simulate, you would now do the same thing, but also run the EDA Netlist Writer to write out a simulation model, and then use that in modelsim. So it's definitely the same change as anyone else complaining about having to go to Modelsim, but it's not like AHDL/Schematic has been dropped.

[Altera_Forum]

Expanding to Rysc's comments, here are some instructions: 

 Setup the path to the Modelsim (or other simulator) executable which can be done by the GUI under Tools>Options>General>EDA Tool Options (This may not be needed with ModelSim Altera Edition). Set simulation options under Assignments>Settings>EDA Tool Settings>Simulation. Select More EDA Netlist Writer Settings. Turn on Generate netlist for functional simulation and any other options you want.  Then Start Analysis and Synthesis. Then Start EDA Netlist Writer.  For more on Simulation, read qts_qii5v3_01.pdf (http://www.altera.com/literature/hb/qts/qts_qii5v3_01.pdf). As I scan through the document, it is clear to me that the document is not very easy to read for somebody without a lot of experience with different EDA tools. It is clear that Altera needs a simpler document/tutorial to describe how to use the ModelSim Altera edition, hopefully showing that it is not that much harder than the old native tool.  As for the claims that BDF and/or TDF is going away, all I can say is that Altera has no plans to do so. Too many of our own regression tests are written in BDF and TDF so for sure it is easier to support these languages than to migrate all our tests :-)   As demonstrated by us bringing back LPM Megafunctions in V10.1, Altera cares about every customer, large or small, and reads and reacts to feedback in this forum. I don't know if we will even bring the simulator back, but for sure we will look into improving our GUI and documentatiton to try to improve the user experience for the cases described in these posts.

[Altera_Forum]

Davka and Rysc, thank you both for your inputs to the AHDL simulation dilemea. I tried Davka's instructions, but they didn't go far enough for me. I'm a hardcore native simulator guy - have been for 15 years - and have never used ModelSim before. For this no-talent *** clown, what do I do after the netlist writer? Do I need to set up NativeLink? If so, what's my testbench file (assuming I don't have one yet because I'm going to be creating one in ModelSim's waveform editor)? What would be of enormous benefit to me (and maybe to some other floundering ModelSim users out there) would be step by step instructions for doing a functional simulation of the following simple AHDL AND gate code: 

 SUBDESIGN SimpleAHDL_ANDforModelSimTest  (  in[1..0] :INPUT;    out :OUTPUT; )    BEGIN  out = in[0] AND in[1]; END;  Davka et al, what am I supposed to do next to get this going in ModelSim? Remember, I just want a functional simulation, and I don't want to explicitly write a testbench file. I want to essentially create my testbench file using ModelSim's waveform editor (just like the good ol' Altera native simulator). Ideas?  Thanks -  -Dano-

[Altera_Forum]

Hi, 

 We are looking at writing a document to explain very simple instructions for BDF/TDF users, but this will take some time. For now, see if this document helps you. You may also want to read the other document I included in my previous post.  You should be able to follow it up, but instead of loading the sample V file, load the V files from your /simulation directory.  ftp://ftp.altera.com/up/pub/altera_material/9.1/tutorials/verilog/modelsim_gui_introduction.pdf (ftp://ftp.altera.com/up/pub/altera_material/9.1/tutorials/verilog/modelsim_gui_introduction.pdf)  Hope this Helps