NIOS II Performance

[Altera_Forum]

What is the fastest clock speed that I can expect to run on a NIOS II processor ? How dependant is this on which chip I choose ?

[Altera_Forum]

http://www.altera.com/literature/ds/ds_nios2_perf.pdf (http://www.altera.com/literature/ds/ds_nios2_perf.pdf)

[Altera_Forum]

<div class='quotetop'>QUOTE (BadOmen @ Jul 17 2009, 12:02 PM) <{post_snapback}> (index.php?act=findpost&pid=23158)</div> 

--- Quote Start ---  http://www.altera.com/literature/ds/ds_nios2_perf.pdf (http://www.altera.com/literature/ds/ds_nios2_perf.pdf)[/b]  --- Quote End ---   BadOmen, thank you for that source. It provided me with a lot of good information. Could you possibly clarify something about Fmax. As the name suggests I understand it is the Maximum Clock frequency (of the system\design), but how does this relate to my NIOS system ? For e.g. does it represent lets say the frequency I can expect my NIOS to run at for a given clock frequency - i.e. If I connect a 200 MHz clock out of my PLL into my NIOS II clock input and the Fmax is 100 MHz - then I can only expect that my NIOS will run at 100 MHz ? For e.g. in the document that you referred to, it states that the Fmax of a ArriaII Gx FBGA is 230 MHz - does that mean that no matter how high I raise the clock connected to the NIOS I can not expect it to run (at the best) more than 230 MHz ?

[Altera_Forum]

Quartus tells you what FMax your design would run at with the setup you entered with these ip functionality you added. 

 As far as i had understand the Altera docs about the possible Fmax for a certain device or family. this FMax is possible but the more ip functionality or logic you add the lower FMax will be. Also it is not realy clear to me how this nios design is setup including everything to get these results. but is possible to reach the range Altera mentioned.   so you are right if Altera says 200 MHz is possible, but your quartus tells you 100MHz. So your fpga design under these conditions will not run safe with a higher frequency. of course there are some "tricks" you could do to speed up your design.   you could also be shure that the the fmax Altera mentiones is the highest possible for this device. if Altera does not know how to get more than your 230MHz who else would know ?  fmax depends on the timing you can reach with your design. the timing depends on output settle time, logic equation time and some input timing (all inside your fpga f.e.) now the logic between 2 Flip Flops must be fast enough that the summ of these 3 timings is less than 1/Fmax you desire. if the summ takes more time then the clock edge will clock your flip flop but the input is not ready, hope that helps to understand why you cann&#39;t increase your clock.  

[Altera_Forum]

yes agreed, as question on both forums sometimes are quartus and sometime nios related and might be interesting for both forums. 

also questions about sdram for example posted here but have been so often answered on nios forum would be within one forum ... i guess combining them both to one is the way to go as nios is from altera like quartus too.  _____________________________________ Website I designed for cash advance halifax (http://www.paydaytown.com) company.