Synchronous Design

[Altera_Forum]

I have got timing problems with a ACEX1K30 Design. To solve my problems I want to change my design in a synchronous design (only one global clock).  

Where can I find examples for synchronous designs?  I use the Quartus (Web-Edition) graphical editor (no VHDL or HDL, sometimes AHDL). I have to realize: Eventcounter (up/down), Ratemultiplier, Frquency-Divider, Monoflop, Timer (Shiftregister), Data Register (from µC).

[Altera_Forum]

I suggest you google with the following words. 

 Verilog Synchronous design or Vhdl Synchronous design  This will provide much help for you.

[Altera_Forum]

I suggest you the vhdl instruction  

if clk'event and clk = 1  the vhdl (or verilog) language guarantee to you about freedom degrees...some things with these graphical tools is much more complicate....  smile stefania:)

[Altera_Forum]

Thank you Avatar, I will try but I think I will have problems with understanding VHDL or Verilog HDL.

[Altera_Forum]

Hi Helmut, 

what kind of Problem you have? What forfrequencies are needed? Do you use you global the Clock Input?In my first Time i wrote also all in AHDL.

[Altera_Forum]

--- Quote Start ---  I have got timing problems with a ACEX1K30 Design.  --- Quote End ---     Even if you're just starting out learning and not doing a design for actual hardware, it is best to use a modern device family. Some Quartus features are not available for old device families, so you won't be able to do everything you could do for an new real design using a recent (or at least more commonly used) device family.  See related comments at "Altera Forums > General > General Altera Discussion > ACEX1k" (http://www.alteraforum.com/forum/showthread.php?t=457&highlight=acex1k).  If I'm just experimenting and not doing something device-specific, I like to choose the smallest device in one of the Cyclone families for quick compile times.