ESD test on cyclone 2

[Altera_Forum]

Hi. 

 We have board designed around Cyclone 2 in 240 pin package(QFP). On this board beside fpga is located memory(DDR RAM) and lvds converters. In the order to done esd test I implemented simple test design which controll LEDs in VHDL and NIOS 2 processor. The processor uses internal memory na lvds links are not used.  So. I perform esd tests( 4KV - 10KV) on our board. It shows that our HDL design + soft processor (NIOS 2) are frequently reloaded duing esd test (also at 4KV). The most frequently reloading is performed when esd test is done around digital power supply (3.3V, 1,2V). I suspect that motion is distributed trough power supply to FPGA, although I have implemented power supply according Altera recommendation.  I would like if anybody has experiences with esd test of cyclone 2 in this package?  Thank you in advance, Amir Hasanovic

[Altera_Forum]

Did you try to add some capacitors, ESD-diods and inductances to/aounrd the pin to find out if there is some influence ?

[Altera_Forum]

Thanx for answer,  

I added few capacitors to filter 3.3V and 1.2V voltages. It results in better operation.   Now, I have to include external memory and m-lvds converters. These could make additional problems during esd test, because of ground debounce...Wrong access to external memory can cause error in nios 2 processor.  ESD diodes are added on the rs232 interface.  Pita

[Altera_Forum]

From here, it is hard to suggest solutions. 

 To me it should be possible to "record" the bahavior of the power lines and signal lines with a oscilloscope when ESD tests are taking place. You might be able then to decice, if it is just an error caused by instable power voltage, as I assume. In case of peeks on the lines, additional suppressor diodes in beneath of the chip might help.

[Altera_Forum]

Pay attesion to the power filters including the power supply for oscillocator.