How can I connect PCI Express MegaCore to FIFO!

[Altera_Forum]

The is some example about conneting PCI Express to SDRAM. 

http://www.altera.com.cn/literature/an/an431.pdf I need to conneting PCI Express to FIFO, I have ask many people engage in FPGA development, but get nothing. SDRAM has address, and can be deal with through DMA. FIFO has no address. How can I connect it to PCI Express? In System Settings, I need to set BAR, but there is no address when I connect PCI Express to FIFO. I will look forward to your response. hedebiao@163.com

[Altera_Forum]

On the PCI Express link you are still going to need an address, any PCI Express Switches in the system need to know how to route requests to your device as opposed to other devices in the system. So you will still need a BAR, you can set it to be the smallest size possible. Your BIOS or OS will assign an address to this BAR and that is the address you will use in your software application to access the FIFO.  

 Now if your endpoint only has the FIFO in it, you can ignore the addresses in your logic design. Any Read and Write requests received from the PCIe link can be used to access the FIFO. If you design it that way then from the software application any address that matches the BAR can be used to access the FIFO.

[Altera_Forum]

Thank you for your reply. 

Avalon-ST Interface and Descriptor/Data Interface are interfaces, which offered by PCI Expresss Compiler. I have read the ports of the interfaces, but find nothing about address. If I don't work in SOPC Builder, how can I distinguish the data from PC?

[Altera_Forum]

Look in the PCI Express Compiler User Guide for version 7.2. Tables 4-30, 4-31, 4-33, 4-34 describe where the PCI Express TLP header (aka descriptor), which contains the address, is located on the Avalon-ST interface. Tables 4-37 and 4-42 describe the location of the TLP Header on the Descriptor/Data interface. Appendix A briefly shows the TLP Header layout, but you will need to consult the actual PCIe specifications or a PCIe reference book for more detailed definitions of the TLP header fields.

[Altera_Forum]

Thank you for your reply. 

I must write code to analyze rx_desc and make data for tx_desc. I think, PCIE is slave port, when translating data to PC, and PCIE is master port, when PC translate data to some memory on FPGA. Am I right? But when PC want to read some data on FPGA, how can I know the PC is reading? I have not writen any program on PC to read data on FPGA through PCIE. Could you give me some examples?

[Altera_Forum]

Transfer of data can happen in either direction for either a Master (PCIe spec actually uses the term Initiator) or a Slave (PCIe spec actually uses the term Completer).  

 If the FPGA with the PCIe port was a completer only (slave only) the PC could transfer data to the FPGA by using Write operations and the PC could transfer data from the FPGA by using Read operations. Now if the FPGA also has initiator (master) capabilities, then it could transfer data to the PC memory by using writes it initiated. It could transfer data from the PC memory by using reads it initiated.   The example design and testbench created by PCI Express Compiler demonstrates both of these modes of operation.   Unfortunately I don't have any PC software application source code to provide as an example. I think the Altera Stratix II GX PCIe Develoment Kit does have a software application that demostrates this, but source code is not available.

[Altera_Forum]

Thank you for your reply. 

I will try the idea you have told me. Thanks!