Gate level sim - EDA netlist writer won't run

[Altera_Forum]

I'm trying to run gate level simulation in modelsim on my design, but the EDA netlist writer will not run! 

 If I simply start "EDA Gate Level Simulation" then "Analysis & Synthesis" is run (successfully) and then "EDA Netlist Writer" is run, failing with error: Error: Run the Fitter (quartus_fit), followed by the Timing Analyzer (quartus_tan or quartus_sta), before running the EDA Netlist Writer (quartus_eda)  Firstly, if that's required, why isn't it included in the stuff to do when double-clicking "EDA Gate Level Simulation"??? Well, fine, I'll run that then: Fitter completes successfully, TimeQuest completes but one timing requirement isn't met (that's ok, not what I'm testing right now). If I now run "EDA Netlist Writer" it runs "Analysis & Synthesis" again, and then "EDA Netlist Writer" failing with the same error as previously.  No matter how I try, I can't seem to run gate level simulation, has anyone else run into the same problem???

[Altera_Forum]

i'm not sure why double clicking the EDA Gate Level Simulation button in the Tasks window only runs Analysis & Synthesis then the EDA Netlist Writer, but to do a gate level timing simulation you will need to run Analysis and Synthesis, Fitter, (optionally a timing analyser), and the EDA Netlist Writer. 

 even after fitting you can't do a gate level simulation?

[Altera_Forum]

No it simply won't let me! 

 If I run fitter (successfully) and then run netlist writer, analysis & synthesis is automatically run first (successfully) and the netlist writer then fails with above message.  Can I run everything manually? Turn off all the automatic choosing of what to run?

[Altera_Forum]

Aaaaaaaaaah, you can run "Compile Design"... 

 Why the same results wouldn't be achievable running them one by one is beyond me.....................................................................................

[Altera_Forum]

--- Quote Start ---  Aaaaaaaaaah, you can run "Compile Design"...  Why the same results wouldn't be achievable running them one by one is beyond me.....................................................................................  --- Quote End ---    Hi,  you need a full compile for the gatelevel simulation, because the simulation includes the timing. The timing information is available after the design is P&R und the timing is analyzed.  Kind regards  GPK

[Altera_Forum]

Yes I understand that you need A&S, Fitter, Timing and Netlist writer to do gate level simulation. The issue is that they can't be run one after another, the absolutely only way (AFAIK) is to realize that you can just double-click "Compile Design". I previously thought that was only a group name in the flow. 

 The error message leads one into thinking you need to run them manually in a specific order, which is impossible. "Compile design" is the only way to do it.