Memory to Device DMA transfer

[Altera_Forum]

Hi, 

 I am working on a byte transfer from SDRAM to a register of my custom hardware. I have set the byte transfer enable and wcon for byte transfers and write to a constant address. But, I see that the DMA is reading from the SDRAM 4 bytes at a time. I dont know about the actual protocol the DMA follows i.e., whether it will read byte - write byte or read word and write it byte by byte. The DMA write master is writing the 1st byte of each word. I am debugging this on modelsim and I see that the byte enable signal is high in the DMA module. The data I am using is 1,2,3,... and DMA is reading 04030201,08070605 etc., and writing 04, 08 etc. (one byte from each read). Can someone help me with this.  Thanks.

[Altera_Forum]

Hi, 

 So your control register before starting the transfer by setting the GO-bit looks like that?  BIT0(BYTE) | BIT4(I_EN) | BIT7(LEEN) | BIT9(WCON)  If so, I would say you'v done it right and I have no idea what is wrong.....   EDIT: Just to be sure. In sopc the DMA is configured to perform byte transfers?

[Altera_Forum]

Yeah, in SOPC the DMA is programmed to perform all the kinds of transfers (byte, hw, word, double word, quadword). The value that I am writing to the control register is 0x2E9. Can you get any insight into the fallacy? 

 Thanks.

[Altera_Forum]

On the first sight I don't see any mistake.  

But why do you have enabled WEEN-bit and REEN-bit? Is there any need for it? And does your component support it? If you use it in software you should enable I_EN-bit as well.  What is the width of your custom hardware register? If it is 32 bit, have you tried to use WORD-transfer instead of BYTE?  If there is no need for performing DOUBLEWORD and QUADWORD-transfers, I would disable it in SOPC.

[Altera_Forum]

Hi, 

 I tried all possible options and was able to narrow down on the problem. If I enable burst transfers in SOPC, I am getting this problem and if I don't enable it is working fine. Can you explain this? Why does the DMA write only a byte of the word if the burst transfer is enable?  Thanks.

[Altera_Forum]

Sorry,  

never used burst mode with DMA. Therefore I don't have an good explanation for you.  Only thing I notice is that in SOPC dma-controller->burst transactions->maximum burst size must be at least 1 word (4 Byte).  So maybe minimal maximum burst size is equal to minimum burst size? (What a strange sentence....;-)) Sorry I am just making a guess. So please, don't take it too serious....  Regards

[Altera_Forum]

--- Quote Start ---  Hi,  I tried all possible options and was able to narrow down on the problem. If I enable burst transfers in SOPC, I am getting this problem and if I don't enable it is working fine. Can you explain this? Why does the DMA write only a byte of the word if the burst transfer is enable?  Thanks.  --- Quote End ---   Hi,  @gangireddy what did you mean with 'enabling burst transfer' and 'disabling burst transfer'? How did you control it? And what was the DMA control register value for both conditions?   Would you post your code here? Now I have problem with DMA but as Rx channel. I have been debugging my DMA for several weeks, but it can't work.... :( I'm sure that it should be easy but I really don't know what the problem with my code. So I hope that you kindly post your code here. Next post, I'll post my code here.