Quartus II Internal Error

[Altera_Forum]

Hi people, 

 compiling a small piece of design, I get the following message:     --- Quote Start ---  Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/verilog/erimisc_elab.cpp, Line: 456 type  --- Quote End ---    Any idea how to deal with it? Thanks in advance.

[Altera_Forum]

Not a clue, but it would help if there's some more information.. Basically you are getting a GPF, of some kind, So opening a support case with Altera is probably the best way to get it resolved. 

 To get help here, we'll probably or through Altera, however, we are going to need more information, including: 1:) Version of Quartus and platform you are using (IE Windows (and version) /Linux (and version), 32-bit/64-bit, etc) 2:) a small sample code that produces the error is ideal (I know not always easy or able to release, but unless someone can reproduce your problem, it's hard to fix the issue)   Other things you can try is: 1:) delete the DB directory and incremental db directories form the synthesis directory and try again. I've seen this fix lots of issues, where a bad or corrupted DB file is causing the issue.  2:) Start commenting the source code out to isolate the section of code causing the issue.   Pete

[Altera_Forum]

Hi anakha, 

 thanks for the answer. It seems like Quartus has a problem with nested interfaces. Small example:  interface data_reg_read_intfc; bit data; bit addr; modport syn_test(input data, output addr); endinterface interface regfile_EXU_intfc (input bit clk, rst); data_reg_read_intfc drr_intfcs (); // bit asd_en; // modport syn_test(input asd_en); endinterface module syn_test(clk, rst, in, out, intfc); input bit clk, rst, in; output bit out; regfile_EXU_intfc intfc; always_ff @ (posedge clk, posedge rst) begin if(rst == 1'b1) begin out <= 1'b0; end else begin out <= in; end end endmodule   It produces this error:    --- Quote Start ---  Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/verilog/verimisc_elab.cpp, Line: 456 type Stack Trace:  0x38b00: vrfx_altera_assert + 0x20 (synth_vrfx)  0x149177: VeriInst::Initialize + 0x77 (synth_vrfx)  0x14e583: VeriModuleInstantiation::Initialize + 0x53 (synth_vrfx)   ...   End-trace   --- Quote End ---    The software version is Quartus II 10.0 sp1, Win7-x64, downloaded yesterday. Quartus 9.1a on a linux machine behaves in the same way.  I'm quite new to SV and maybe I'm doing something wrong, but Modelsim simulates my code properly.  Maybe you can give me a small code example with nested interfaces that works? I would really appreciate it.

[Altera_Forum]

Unfortunately I have zero experience with system verilog.... (Need to get some training on it as soon as I can find a week to go to a class..) 

 But it could be one of the following: Nested interfaces aren't supported yet in synthesis.. (it should catch it earlier in the compile stage and tell you though).  Or your uses of () is confusing it.. Try changing   interface data_reg_read_intfc;  bit [15:0] data;  bit [3:0] addr;   modport syn_test(input data, output addr); endinterface    interface regfile_EXU_intfc (input bit clk, rst);    data_reg_read_intfc drr_intfcs ();  // bit asd_en; // modport syn_test(input asd_en);   endinterface  to   interface data_reg_read_intfc;  bit [15:0] data;  bit [3:0] addr;   modport syn_test(input data, output addr); endinterface    interface regfile_EXU_intfc;  bit clk, rst;  data_reg_read_intfc drr_intfcs ();  // bit asd_en; // modport syn_test(input asd_en);   endinterface   It's a minor difference, but may be the source of this issue.. I don't know if what you did was valid or not..

[Altera_Forum]

One other thing you may want to try.. 10.1 just got released.. A pain to download the 7 GB iso, but it may be worth a shot..

[Altera_Forum]

Hi anakha, 

 the new, 10.1 version, doesn't behave better, and no changes help. Except of this, the interface arrays are supported in a some strange way. Well, I'll have to make my design without any extensive use of interfaces. Actually it's a pity... Thanks nevertheless.

[Altera_Forum]

BTW, I found an interesting bug today: 

 package parameters; parameter int number_of_ALU_types = 1; parameter int num_data_read_intfcs = '{2}; endpackage import parameters::*; module ALU_wrapper (clk, rst); input bit clk, rst; parameter int ALU_type = 0; parameter int num_data_read_intfcs = num_data_read_intfcs; //this line is critical endmodule  The reason is - the name of the parameter in the critical line is equal to the name of the array in the package. Modelsim has no problems with it, but Quartus generates stack overflow critical error. Hopefully my post would prevent somebody from doing the same mistake:)

[Altera_Forum]

andyv51 where did you read that interface arrays are supported ? (http://www.alteraforum.com/forum/member.php?u=39921) 

  What is the synthax ?

[Altera_Forum]

--- Quote Start ---  AndyV51 where did you read that interface arrays are supported ?   --- Quote End ---    Nowhere. I had some in my design, and Quartus didn't complain about them. But, if it supports them at all, it does it in a very strange manner.  Some example code:  interface reg_sigs_ifc; bit in; bit out; modport regs(input in, output out); endinterface module regs(clk, rst, en, reg_sigs); parameter num_regs = 6; input bit clk, rst, en; reg_sigs_ifc reg_sigs; //interface array bit in; bit out; genvar i; generate for(i = 0; i < num_regs; i++) begin: gen_regs assign in = reg_sigs.in; assign out = reg_sigs.out; end endgenerate always_ff @ (posedge clk, posedge rst) begin if(rst == 1'b1) begin out <= '0; end else begin if(en == 1'b1) begin for(int i = 0; i < num_regs; i++) begin out <= in; end end end end endmodule  This example compiles successfully by Quartus, but no registers are generated. So I prefer not to use such constructs.