Most FPGA designs today are largely synchronous circuits controlled by clock networks. These clock networks are typically composed of both externally generated clocks (Absolute Clocks) and internally generated clocks (Gated and Derived Clocks). The focus of this Tech Note is the latter, internally generated clocks. The various types of both Gated Clocks and Derived Clocks are discussed, with recommendations for their implementation in Altera FPGAs, and their timing analysis. Many of the more complex clock networks are difficult if not impossible to time properly in the Classic Timing Analysis engine; however Altera’s TimeQuest Timing Analyzer handles these situations easily when constrained properly. The proper method of designing and constraining internally generated clocks is the main focus of this Tech Note.
