generate clock with Quartus 7.1 web adition

[Altera_Forum]

Hello everyone, 

 I'm a new quartus user, and I need to generate a clock with the FPGA. the clock frequency should be 200MHz, and it will drive another device, so it has to be an output. i'm using verilog if it makes any difference.  Can anyone tell me how to do that?

[Altera_Forum]

You cannot generate a clock just by using the FPGA internal constructs. 

You can bring into the FPGA a slower (or faster) clock and connect to a PLL and generate the desired 200 MHz output you desire.

[Altera_Forum]

Thanks for your reply. 

 So if I'll take a clock from another device, which is slower, what should I do to connect it to a PLL to generate 200MHz?  Does it matter if the input clock is much slower (about 100-150Hz)?

[Altera_Forum]

Please refer to the Users Guide for the target FPGA family you are looking to use. 

Cyclone, Cyclone II, Arria GX, Stratix, Stratix II(GX), Stratix III.  In there, you will find a discussion on PLL usage and information on allowable minimum input frequencies.