Re: Problem delay

Altera_Forum · ‎06-24-2009

I have some problems with a project.

In my project there are more inverter chained (chain of inverters).

During the compilation, the sinthesis consider only one inverter if the inverters are odd, and 2 inverters if the inverters are even.

So i decided to put every single inverter in a own lut.

The problem is solved, but is it the only possibility?

If i don't put the inverters in more luts,the too put all the project in a single lut, but so can i modify the path of the chain of inverters to increase the delay?

Altera_Forum · ‎06-24-2009

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In my project there are more inverter chained (chain of inverters).

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It is natural that the synthesizer removes unneeded inverters.

Why would you like to build a chain of inverters?

Are you intending to build a ring oscillator?

Altera_Forum · ‎06-24-2009

even though its dirty, i have done this in VHDL using the keep attribute:

library ieee;
use ieee.std_logic_1164.all;
entity keeplogic is
    port(
        insig         : in        std_logic;
        outsig         : out        std_logic;
        outkeep        : out        std_logic
        );
end keeplogic;
architecture rtl of keeplogic is        
signal sig_wire        :            std_logic;
signal keep1_wire    :            std_logic;
signal keep2_wire    :            std_logic;
signal keep3_wire    :            std_logic;
signal keep4_wire    :            std_logic;
signal keep5_wire    :            std_logic;
signal keep6_wire    :            std_logic;
attribute keep: boolean;
attribute keep of keep1_wire: signal is true;
attribute keep of keep2_wire: signal is true;
attribute keep of keep3_wire: signal is true;
attribute keep of keep4_wire: signal is true;
attribute keep of keep5_wire: signal is true;
attribute keep of keep6_wire: signal is true;
begin
    --does not preserve not gates
    sig_wire <= not( not( not( not( not (not insig)))));
    
    --does preserve not gates
    keep1_wire <= not insig;
    keep2_wire <= not keep1_wire;
    keep3_wire <= not keep2_wire;
    keep4_wire <= not keep3_wire;
    keep5_wire <= not keep4_wire;
    keep6_wire <= not keep5_wire;
    
    outsig <= sig_wire;
    outkeep <= keep6_wire;
end;

Altera_Forum · ‎06-24-2009

Yep. Synthesis reduces logic that doesn't affect the RTL behavior. (This is usually a good thing, and when you don't want it done, you're usually doing a "non-standard" design.) You probably already know that, and there are cases where a ring-oscillator will do the job. (I've done a similar design but put an LCELL primitive after each NOT gate. This is easier in schematic, where thepancakes is better in HDL.

Make sure you time it correctly, which is difficult since it's not a synchronous structure, and the whole concept of static timing analysis is based on synchronous clocks. You may already know this, but there are slow and fast timing models, and your ring oscillator will be anywhere in between. So if the ring delay is 10ns in the slow model, it might be 5ns in the fast model. That means your loop delay is varying between 100MHz and 200MHz(half that for a full clock period). This is why uncalibrated ring oscillators are not used very often.

Altera_Forum · ‎06-25-2009

Yes, i'm doing a ring oscillator. I have solved the problem with Lcell and i declare every single inverter with lcell.

The problem is that Lcell have 1 input and i want to declare also other logic gate (ex. and2, or2 etc) as Lcell.

In this way i need 2 lcell to declare a single and2 gate.

Is it true?

Altera_Forum · ‎06-25-2009

No. An LCELL states that that point is the output of a logic cell. If you feed it an AND gate, then it gets absorbed into that LUT and the LCELL is still the output.