Problems setting up LVDS on CycloneIII

[Altera_Forum]

Hi there, 

 I'm trying to set up a 16x2 bit LVDS connection with a CycloneIII device. The actual model I'm using is the EP3C16Q240C8N.  First, I'm verifying my config in the Quartus pin planner. For this, my design only contains a simple LVDS block I made with the MegaWizard. Up till now, I've have found 2 problems in the pin planner:  - When I assign a LVDS signal to pin 7, which is a diff pin in bank 1, I get this error: error: the transmitter driving i/o pin outdata[0] at data rate 839 mbps exceeds the maximum allowed data rate of 640 mbps for lvds output Although the CycloneIII handbook clearly states on page 8-3 that banks 1,3,5,6 should support speeds of up to 840MHz! How come Quartus complains the device can only work at max 640MHz? This would be so uncool! Even my grandma can transition at higher speeds.  - No problem, I changed the megawizard to 640Mbps. Next problem: I cannot use pins of bank 1 for LVDS, because I cannot change its voltage to 2.5V!  "error: pin outdata[0] is incompatible with i/o bank 1. it uses i/o standard lvds, which has vccio requirement of 2.5v. that requirement is incompatible with bank's vccio setting or other output or bidirectional pins in the bank using vccio 3.3v." There's no way I can change the VCCIO for bank 1 in the pin planner, although I can alter the VCCIO for the other banks. This is most likely caused because the config device needs to be connected to that bank. So I went to the device configuration options, but there NO WAY to set the VCCIO of bank 1 to 2.5V. While I definately need a serial config device in my design ... They specifically designed bank 1 for hi-speed LVDS, but it isn't compatible with LVDS voltages ???  So 2 questions:  - How to get 840Mbps out of banks 1,2,5 and 6?  - How to make bank 1 work with LVDS?  Any help is MUCH appreciated! Riemer

[Altera_Forum]

Some properties are defined by Cyclone III hardware and can't be changed: 

 1. LVDS I/O needs VCCIO of 2.5V  2. Configuration interface is located in bank 1 3. -8 speed grade has maximum LVDS output data rate of 640 MHz  Additionally, Altera doesn't supply AS configuration devices with supply voltage below 3.3V Also the manual suggests not to use level converters at AS interface and VCCIO level of 2.5V isn't specified to drive 3.3V IO-standards on output.  As a result, your design can't work with LVDS in bank 1 if the other requirements have to be kept.  Some conclusions: -To use 840 MHz LVDS with specified performance, you have to use -6 speed grade.  -You must either move LVDS IO to another bank or find a way to use AS configuration with VCCIO of 2.5V. The most simple solution is to connect EPCS supply to 3.3V but operate the device in the 2.5V bank. To use AS configuration, it's not necessary to specify AS configuration in Quartus, only MSEL must be pin strapped correct, so you can specify VCCIO of 2.5 and connect an AS device anyway. Cause these method isn't supported by Altera officially, you have to verify correct operation on your own. -Other options would be: using level converters or EPCS compatible serial flash with 2.5V supply from other manufacturers

[Altera_Forum]

Well I REALLY want to thank you for this answer! 

 I had no idea the speed grade also influences maximal IO speeds. Unfortunately, the -6 grades are only available on BGA packages, which we cannot solder ourselves on prototyping boards. But at least now we know what is the limiting factor.  Your suggestions on operating the bank at 2.5V and leaving the VCC for the rom at 3.3V is also most useful. I'll make the bank IO voltage selectable in case things go wrong after all.  Thanks again!

[Altera_Forum]

In addition, I don't know what a speed grade for Altera FPGA actually means. Most likely, there is a selection of wafers in production, but it's not excluded, that an individual -8 chip is capable of 840 MHz, so a prototype may operate. The fact that, -6 isn't available in PQFP (I wasn't aware of yet) possibly indicates reduced signal quality expectable with this package. This is known at least regarding ground bounce and SSO noise issues and is also reflected by some IO placement rules. 

 Good luck.