Re: Verilog simulation

Altera_Forum · ‎07-23-2010

I wonder if what I've in mind is possible.

Imagine I've a 64bit counter that rolls to 0 when the count is 64'hFFFFFFFFFFFFFF0. The counter is described in Verilog code.

The counter has no signal to load a particular counter value.

I want to simulate counter behaviour and test if it resets when expected.

I don't want to simulate 2^64 clock cycles foroabvious reasons.

Is there a way to write a tesbench that, at a certain simulation point,

sets a particular value in the register of the counter?

My question is then:

is it possible, in simulation, to set a particular state in the circuit under test?

As example, is it possible to put a finite state machine in a not defined state, to check it's behaviour?

Thx for your help.

P.S. Is this the correct forum for Verilog questions?

Do you know a more adequate one?

Altera_Forum · ‎07-23-2010

you can take a look at the ModelSim force command, or right click the signal in the Objects window to look for the Force window

Altera_Forum · ‎07-28-2010

I solved the problem using Verilog.

The command that should be used is 'force' followed by 'release'.

Here's a snmipset of the code:

 
initial
begin
reset=1;{read_write, ready, write_OK}=3'b000;# period;
reset=0;{read_write, ready, write_OK}=3'b000;# (2*period);
{read_write, ready, write_OK}=3'b010;# period;
{read_write, ready, write_OK}=3'b001;# period;
// ac_state is the name of the internal node
force UUT.ac_state = 5'b00000;# period; 
release UUT.ac_state;# (3*period)
$stop;
end
endmodule

Altera_Forum · ‎07-28-2010

thanks for the tip