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Icon | Title | Posts | Recent Message Time Column |
---|---|---|---|
Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
| 95783 Posts | 05-24-2024 09:35 PM | |
FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
| 29062 Posts | 05-24-2024 04:36 AM | |
FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
| 27593 Posts | 05-25-2024 10:50 PM | |
Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises
| 4984 Posts | 05-21-2024 02:11 AM | |
Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, FPGA AI Suite, Software Stack, and Reference Designs
| 2540 Posts | 05-24-2024 12:59 PM | |
Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
| 52856 Posts | 05-24-2024 05:52 AM | |
Intel® SoC FPGA Embedded Development Suite
Support for SoC FPGA Software Development, SoC FPGA HPS Architecture, HPS SoC Boot and Configuration, Operating Systems
| 2556 Posts | 05-25-2024 01:00 AM | |
Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
| 82918 Posts | 05-25-2024 11:22 PM | |
Intel® High Level Design
Support for Intel® High Level Synthesis Compiler, DSP Builder, OneAPI for Intel® FPGAs, Intel® FPGA SDK for OpenCL™
| 3595 Posts | 05-23-2024 07:42 AM | |
Intel® FPGA Software Installation & Licensing
Installation and Licensing that’s includes Intel Quartus® Prime software, ModelSim* - Intel FPGA Edition software, Nios® II Embedded Design Suite on Windows or Linux operating systems.
| 5765 Posts | 05-22-2024 09:31 PM | |
FPGA Wiki
Welcome to the Intel FPGA Wiki
| 364 Posts | 11-03-2022 01:29 PM |
by DmitryKo Beginner in Intel® Quartus® Prime Software 05-25-2024 0 2 | 0 | 2 | ||
0 | 0 | |||
by terecatu New User in Intel® Quartus® Prime Software 05-25-2024 0 3 | 0 | 3 | ||
0 | 5 | |||
by CAlex New Contributor II in Intel® SoC FPGA Embedded Development Suite 05-25-2024 0 0 | 0 | 0 | ||
by Pack_of_lone_wolves New Contributor I in Intel® Quartus® Prime Software 05-25-2024 0 17 | 0 | 17 | ||
0 | 20 | |||
by RubenPadial New Contributor I in Application Acceleration With FPGAs 05-24-2024 0 20 | 0 | 20 | ||
by dhuynh1 Beginner in FPGA, SoC, And CPLD Boards And Kits 05-24-2024 0 2 | 0 | 2 | ||
by ricj Novice in FPGA, SoC, And CPLD Boards And Kits 05-24-2024 0 1 | 0 | 1 | ||
0 | 2 | |||
by Yevpator Beginner in Nios® V/II Embedded Design Suite (EDS) 05-24-2024 0 0 | 0 | 0 | ||
by Oliver_I_Sedlacek New Contributor III in Nios® V/II Embedded Design Suite (EDS) 05-24-2024 0 0 | 0 | 0 | ||
by number_7 Beginner in FPGA Intellectual Property 05-24-2024 0 5 | 0 | 5 | ||
by NaGPT Beginner in Intel® Quartus® Prime Software 05-24-2024 0 4 | 0 | 4 |
Routing constraints in QPP by Pack_of_lone_wolves 05-25-2024 0 17 |
Cyclone® V FPGA – Remote System Upgrade over UART Based on Nios® II Processors with EPCQ Design Exam by manishkumar 05-24-2024 0 16 |
Problem with CXL IP Design Example Type 3 on DK-DEV-AGI027RBES by xalverti 05-22-2024 0 13 |
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