I am trying to use SerialLite II at the 3Gpbs rate. There are a number of possible choices for the clock frequency ranging from 62.5 MHz all the way to 156.2 MHz.
1- Since all of these frequencies will work, what is the advantage to using one versus the other? I would rather use the lower clock speeds if possible.
2- Can I use that same clock for the rest of the design or is there a reason to add a separate oscillator/clock on a different input to the FPGA? So far Quartus is ok with having one clock drive the SerialLite block and the rest of the logic. In either case, I have to use dcfifos to cross to the SerialLite Tx/Rx domains.
Thank you so much for any insight on this.
