ALTLVDS pin parametres in assignment editor

[Altera_Forum]

Hello everybody, I have a probleme with my project, I have generated a ALTLVDS witha a external PLL megacore, I add an ALTIObuf iorder to have two outputs (lvds_out+ and lvds_out-) I simulate every things is ok but when I start to assigne the pins in pin editor I put the location an for the I/O standard I use LVDS and when compiling I have this error : 

error : pin H3 does not support I/O standard LVDS for lvds_out[0] error : pin H3 does not support I/O standard LVDS for lvds_out[1] I am using quartus 10.1 plse helppppppppppp

[Altera_Forum]

nobody is here??? ^plse, it's been 4 days that I have this problem

[Altera_Forum]

You'll only ever get responses if you provide enough information. 

 You have not stated the part number you are using.  You have not stated that you have confirmed that the I/O pad you are assigning supports LVDS.  The error is telling you that the pin H3 can not be used for LVDS:  "error : pin H3 does not support I/O standard LVDS"  So go and read the data sheet and see if that truly is the case. You can use general purpose I/O pins to emulate LVDS, but it requires an external resistor network.  Cheers, Dave

[Altera_Forum]

Hello, I am so sorry, I am just new in this forum, and my english is not so good that's why I was not so clear. 

I am using quartus 10.1 and stratix iv GX I am working on a project to realize a DVI interface using serdes. I did all my blocs using sopc builder and megawizard. on my output I must have 8 chennels of outputs (chR+, chR-, chB+, chB-, chG+, chG-) of one bit each one. I used the ALTLVDS for the serdes then i had 4 outputs, and to have the (-) and the (+) for each one I used ALTIOBUF. When I assigned the pins name in the assignement editor I don't know which caracteristic I must have to this pins. hope I was clear and thank you a lot for your replay. :)

[Altera_Forum]

Hi bourazza, 

   --- Quote Start ---  Hello, I am so sorry, I am just new in this forum, and my english is not so good that's why I was not so clear.   --- Quote End ---  Your English is just fine, as I commented, you didn't tell us what you had tried already.    --- Quote Start ---   I am using quartus 10.1 and stratix iv GX I am working on a project to realize a DVI interface using serdes. I did all my blocs using sopc builder and megawizard. on my output I must have 8 chennels of outputs (chR+, chR-, chB+, chB-, chG+, chG-) of one bit each one. I used the ALTLVDS for the serdes then i had 4 outputs, and to have the (-) and the (+) for each one I used ALTIOBUF. When I assigned the pins name in the assignement editor I don't know which caracteristic I must have to this pins. hope I was clear and thank you a lot for your replay. :)  --- Quote End ---  You haven't stated which physical pins on the device you have tried.  You didn't state exactly which Stratix IV GX device part number you are using.  The answer to your question can be found in the pin connections guideline spreadsheet found on the Altera web site;  http://www.altera.com/literature/dp/stratix4/pcg-01005.pdf  and in the pinout for your specific part number:  http://www.altera.com/literature/lit-dp.jsp?category=stx%204&showspreadsheet=y  You need to check which pins are capable of operating with LVDS logic levels.  Is this a custom board, or an Altera kit? If it is an Altera kit with an HSMC connector, then pins on that connector have been defined LVDS operation eg., see the Stratix IV GX development kit.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  error : pin H3 does not support I/O standard LVDS for lvds_out[0] error : pin H3 does not support I/O standard LVDS for lvds_out[1]  --- Quote End ---   Sounds like two pins are assigned to the same location, which would be an error on it's own.    --- Quote Start ---  I used the ALTLVDS for the serdes then i had 4 outputs, and to have the (-) and the (+) for each one I used ALTIOBUF. When I assigned the pins name in the assignement editor I don't know which caracteristic I must have to this pins. hope I was clear and thank you a lot for your replay.  --- Quote End ---   As discussed in many similar threads, you don't need an ALTIOBUF primitive to assign LVDS in- or outputs. Just assign an LVDS IO standard to the non-inverted pin of a differential pair. Quartus will supplement the inverted pin assignment automatically.  Stratix family FPGA have dedicated LVDS in- and output drivers. You can only assign one of the dedicated drivers. The Quartus Pin Planner can ease this operation, because it knows about available pin locations.

[Altera_Forum]

Tahnk you both of you, I realy apreciate it, I am using stratix iv (EP4SGX230KF40C), I remove the altiobuf, you are right. 

now I juste use the non inverted pins that I assign IO standard to LVDS but I still have the same errors : Error: Pin H4 does not support I/O standard LVDS for dataG_o[0] Error: Pin V4 does not support I/O standard LVDS for dataR_o[0] Error: Pin F4 does not support I/O standard LVDS for dataB_o[0] Error: Pin AM4 does not support I/O standard LVDS for dataCLK_o[0] Error: Pin H3 does not support I/O standard LVDS for dataG_o[0](n) Error: Pin V3 does not support I/O standard LVDS for dataR_o[0](n) Error: Pin F3 does not support I/O standard LVDS for dataB_o[0](n) Error: Pin AM3 does not support I/O standard LVDS for dataCLK_o[0](n) :s I don't know what to do... I will try to re-read the data sheet.

[Altera_Forum]

I see, that all selected pin pairs are dedicated transvceiver pins of EP4SGX230KF40C. Refer to the pinout file or use the Quartus Pin Planner tool to choose suitable pins that support the LVDS standard as output.

[Altera_Forum]

When I try to put something else than the LVDS like the PCML I have the folowing errors : 

Error: Can't place differential I/O pin dataG_o[0] with differential I/O standard 1.5-V PCML -- differential I/O pin dataG_o[0] drives or is driven by a SERDES Error: Can't place differential I/O pin dataR_o[0] with differential I/O standard 1.5-V PCML -- differential I/O pin dataR_o[0] drives or is driven by a SERDES Error: Can't place differential I/O pin dataB_o[0] with differential I/O standard 1.5-V PCML -- differential I/O pin dataB_o[0] drives or is driven by a SERDES Error: Can't place differential I/O pin dataCLK_o[0] with differential I/O standard 1.5-V PCML -- differential I/O pin dataCLK_o[0] drives or is driven by a SERDES Error: Can't place differential I/O pin dataG_o[0](n) with differential I/O standard 1.5-V PCML -- differential I/O pin dataG_o[0](n) drives or is driven by a SERDES Error: Can't place differential I/O pin dataR_o[0](n) with differential I/O standard 1.5-V PCML -- differential I/O pin dataR_o[0](n) drives or is driven by a SERDES Error: Can't place differential I/O pin dataB_o[0](n) with differential I/O standard 1.5-V PCML -- differential I/O pin dataB_o[0](n) drives or is driven by a SERDES Error: Can't place differential I/O pin dataCLK_o[0](n) with differential I/O standard 1.5-V PCML -- differential I/O pin dataCLK_o[0](n) drives or is driven by a SERDES

[Altera_Forum]

The SERDES pins can only be used with the ALTGX megafunction. The transmitters are PCML, while the receivers can operate with PCML or LVDS. 

 You cannot use them as a general purpose LVDS pin. However, it might be possible to use them for your application; it just depends on what that application is.  Cheers, Dave

[Altera_Forum]

Thank you FvM for your replay. How can I khew which pin support lvds?

[Altera_Forum]

The problem is that all the pins are given to me I can't change them. And the problem is what to put in assignment editor apart from the location? (I/O standard, termination....) because I don't know what to add else, I am so sorry I am asking a lot of questions :$

[Altera_Forum]

--- Quote Start ---   How can I knew which pin support lvds?  --- Quote End ---    The references I provided links to tell you.  Please make an attempt at reading the documentation people helpfully supply you, otherwise you will find that you will stop getting responses.   Cheers, Dave

[Altera_Forum]

--- Quote Start ---  The problem is that all the pins are given to me I can't change them. And the problem is what to put in assignment editor apart from the location? (I/O standard, termination....) because I don't know what to add else, I am so sorry I am asking a lot of questions  --- Quote End ---  Please describe what you are trying to communicate with over these pins.  How do you know the standard needs to be LVDS?  Is the link to the device you are communicating with AC or DC coupled?  Can you provide the data sheet of the device?  How about schematics of the FPGA board you are using?  Cheers, Dave

[Altera_Forum]

Hi, 

Thank you for your replay and your help, you were right, I changed the altlvds to altgx because of the pins chosen. and now it works thank you again :)

[Altera_Forum]

--- Quote Start ---   ... now it works ...   --- Quote End ---    Great!  Cheers, Dave